Abstract: An apparatus includes a plurality of memory die and a controller coupled to the plurality of memory die. The controller is configured to selectively process a plurality of random read commands in such a way to reduce a total time required to execute the random read commands.

Abstract: Aspects of a storage device are provided which allow for identification of control page patterns from previous read commands and prediction of control pages to load in advance for subsequent read commands. The storage device includes a memory configured to store data and a plurality of control pages. Each of the control pages includes a plurality of logical addresses associated with the data. A controller is configured to receive from a host device a plurality of read commands associated with a sequence of the control pages. The controller is further configured to identify and store a control page pattern based on the sequence of control pages and to predict one or more of the control pages from one or more of the other control pages in the sequence in a subsequent plurality of read commands.

Abstract: Aspects of a storage device are provided which allow a read command to be identified for execution from multiple read commands received from a host. The storage device includes a memory configured to store a plurality of data units each comprising one or more data fragments, and metadata associated with the data units. A controller is configured to receive from the host a plurality of read commands each requesting one of the data units. The controller is further configured to identify one of the read commands based on the metadata, and to transfer the data unit associated with the identified read command to the host before transferring the data unit associated with the other read commands.

Abstract: A memory device operable in either of a Secure Digital operational mode and an NVMe operational mode includes password conversion logic to enable the memory device user-mode memory blocks to be accessed in the NVMe operational mode after the memory device was locked in the Secure Digital operational mode.

Abstract: A memory device operable in either of a Secure Digital operational mode and an NVMe operational mode includes password conversion logic to enable the memory device user-mode memory blocks to be accessed in the NVMe operational mode after the memory device was locked in the Secure Digital operational mode.

Abstract: In a non-volatile memory system, such as flash memory, when selecting a block for write operation, the system selects blocks from a free block list (FBL). The memory circuits of non-volatile systems often experience cluster failures, where multiple blocks of a physical region are bad. If the free block list is loaded with blocks from a region having a cluster failure, this can result in multiple back to back write errors. To help avoid this situation, the blocks of a memory array are divided into physical zones and, when selecting blocks to replenish the free block list, blocks are chosen cyclically from the zones.

Abstract: In a non-volatile memory system, such as flash memory, when selecting a block for write operation, the system selects blocks from a free block list (FBL). The memory circuits of non-volatile systems often experience cluster failures, where multiple blocks of a physical region are bad. If the free block list is loaded with blocks from a region having a cluster failure, this can result in multiple back to back write errors. To help avoid this situation, the blocks of a memory array are divided into physical zones and, when selecting blocks to replenish the free block list, blocks are chosen cyclically from the zones.