Patents by Inventor Dinesh Kumar Agarwal

Dinesh Kumar Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11429663
    Abstract: A storage system and method for host-assisted memory block color coding for faster media search are provided. In one embodiment, a controller of the storage system is configured to receive an image and color properties of the image from a host and store the image in an area of memory associated with the color properties. Other embodiments are provided.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: August 30, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Dinesh Kumar Agarwal
  • Patent number: 11422734
    Abstract: Storage devices can be configured to desirably reduce the number of times a zone reset or erasure occur via the use of one or more paired overwrite memory blocks. These storage devices can include a plurality of memory devices with some of these memory devices designated as overwrite memory devices. A controller within the storage device can be configured to direct the storage device to generate one or more subsets within the memory devices such as zones, pair each of subsets with at least one or more overwrite memory devices, store data sequentially within the subset of memory devices, and store any received overwrite data in the overwrite memory devices in chronological order. Data stored within the subsets of memory devices are not erased and instead of being overwritten directly, are instead pointed via a control table to a location in the overwrite memory devices storing the corresponding overwrite data.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: August 23, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Dinesh Kumar Agarwal
  • Patent number: 11416176
    Abstract: Systems and methods for distributed storage and processing systems using storage controllers for load sharing are described. A host processor may receive a function request that corresponds to a plurality of compute tasks, such as map compute tasks targeting data in local storage. The host processor may fetch the data from local storage devices through storage controllers. At least one storage controller, such as a non-volatile memory express (NVMe) interface controller, may be configured to execute overflow tasks for the function request. Another storage controller may be configured for executing other processing and management activities, such as reduce compute tasks.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: August 16, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Dinesh Kumar Agarwal
  • Patent number: 11416166
    Abstract: Systems and methods for distributed storage and processing systems using estimate-based schedulers are described. A node receives estimated processing data for each storage device including redundant copies of data chunks for a data unit. The node determines, based on the estimated processing data and data paths to each data chunk, a task time estimate for data paths to each data chunk and selects data paths for at least one copy of each data chunk to be processed using a corresponding set of compute tasks. The compute tasks are sent for processing based on the assignments of the node.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: August 16, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Dinesh Kumar Agarwal
  • Publication number: 20220214824
    Abstract: Storage devices can be configured to desirably reduce the number of times a zone reset or erasure occur via the use of one or more paired overwrite memory blocks. These storage devices can include a plurality of memory devices with some of these memory devices designated as overwrite memory devices. A controller within the storage device can be configured to direct the storage device to generate one or more subsets within the memory devices such as zones, pair each of subsets with at least one or more overwrite memory devices, store data sequentially within the subset of memory devices, and store any received overwrite data in the overwrite memory devices in chronological order. Data stored within the subsets of memory devices are not erased and instead of being overwritten directly, are instead pointed via a control table to a location in the overwrite memory devices storing the corresponding overwrite data.
    Type: Application
    Filed: February 26, 2021
    Publication date: July 7, 2022
    Inventor: Dinesh Kumar Agarwal
  • Patent number: 11379128
    Abstract: Systems, storage devices, and methods for application-based storage device configuration settings are described. A storage device may receive a storage command and dynamically select an application set of configuration settings for processing the storage command, where the configuration settings include trim parameters for writing data units to the storage medium of the storage device.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: July 5, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dinesh Kumar Agarwal, Amit Sharma
  • Patent number: 11379137
    Abstract: A data storage device including, in one implementation, a non-volatile memory device including a memory block that includes a plurality of memory dies and a controller that is coupled to the non-volatile memory device and that allocates power to non-memory components based on a determined usage of the memory dies. The controller is configured to monitor a utilization of the plurality of memory dies, determine a utilization state of the plurality of memory dies, and calculate an amount of available power allocated to the plurality of memory dies in response to determining that the plurality of memory dies are in a low utilization state. The controller is also configured to determine whether the amount of available power is above a predetermined threshold, and reallocate the available power to one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: July 5, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Abhinandan Venugopal, Dinesh Kumar Agarwal, Akhilesh Yadav
  • Patent number: 11379117
    Abstract: A storage system and method for using host-assisted variable zone speed grade modes to minimize overprovisioning are provided. In one embodiment, a controller of the storage system is configured to receive a request from a host for creation of a zone of memory; in response to the request, create the zone to avoid overprovisioning the zone; determine speed grades of a plurality of usage modes of the zone; inform the host of the speed grades of the plurality of usage modes of the zone; and receive, from the host, a command to write data in the zone pursuant to one of the plurality of usage modes. Other embodiments are provided.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: July 5, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Dinesh Kumar Agarwal
  • Publication number: 20220171558
    Abstract: Non-volatile memory (NVM) dies of a data storage device, wherein on-chip latches of the dies are made available to a host device for use as volatile memory. In some examples, a data storage controller dynamically determines when the latches of a particular NVM die of an NVM array are available for use as volatile memory and exports those particular latches to the host device for use as random access memory (RAM). In other examples, the data storage controller dynamically determines when particular dies of the NVM array of dies are available and exports all latches of those dies to the host device for use as RAM. The data storage controller may rotate NVM die usage so that, over time, different dies are used for latch-based volatile memory while other dies are used for NVM storage. Usage profiles are described that allow the host device to select particular latch usage configurations.
    Type: Application
    Filed: February 24, 2021
    Publication date: June 2, 2022
    Inventors: Amit Sharma, Dinesh Kumar Agarwal
  • Patent number: 11347420
    Abstract: Aspects of a multi-protocol storage device including a memory and a controller are provided which allow for endurance and other storage requirements of a host to be maintained for different logical regions of memory without disruption due to protocol switching. The memory includes blocks that are each associated with a storage attribute such as high endurance, performance, or protection. While operating in a first mode such as NVMe, the controller receives a mapping of storage attributes to different logical regions and stores the mapping in memory. The controller also associates blocks to logical addresses based on the mapping. When the controller switches to a second mode such as SD in response to a host command, the controller reads the mapping from memory and similarly associates blocks to logical addresses based on the mapping in the second mode. Storage attributes thus remain applicable across modes when mapping and storing data.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: May 31, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ramanathan Muthiah, Dinesh Kumar Agarwal, Hitesh Golechchha
  • Patent number: 11314445
    Abstract: Aspects of a storage device are provided which allow for identification of control page patterns from previous read commands and prediction of control pages to load in advance for subsequent read commands. The storage device includes a memory configured to store data and a plurality of control pages. Each of the control pages includes a plurality of logical addresses associated with the data. A controller is configured to receive from a host device a plurality of read commands associated with a sequence of the control pages. The controller is further configured to identify and store a control page pattern based on the sequence of control pages and to predict one or more of the control pages from one or more of the other control pages in the sequence in a subsequent plurality of read commands.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: April 26, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Dinesh Kumar Agarwal, Hitesh Golechchha, Sourabh Sankule
  • Publication number: 20220121367
    Abstract: A resource tracking storage system can track and associate resource usage within storage devices to requesting virtual hosts. Controllers may be configured to receive commands for storage device usage sent from the requesting virtual hosts. Each command for storage device usage may result in a need for future maintenance work to be done within the storage device. Additionally, performance policies, which may be one or more set of rules, thresholds, and/or specifications that indicate a minimum (or maximum) level of performance by the storage device can be regulated by tracking and determining which hosts are degrading the performance of the storage device. With this solution, one or more performance policies can also be enforced by making sure one host is not negatively impacted from the negative storage device usage of another, errant host, even prior to the need for maintenance.
    Type: Application
    Filed: February 22, 2021
    Publication date: April 21, 2022
    Inventor: Dinesh Kumar Agarwal
  • Publication number: 20220113905
    Abstract: Aspects of a storage device including a memory and a controller are provided which re-prioritize commands based on zone properties. The controller receives from a host commands associated with a plurality of zones, allocates the memory into a plurality of zone resources based on zone properties indicated by the host for the zones, and identifies a utilization state of the memory for one of the zones. The controller changes a priority order of the commands based on the zone properties and the utilization state for the one of the zones. The controller then executes the commands in the memory or zone resources according to the priority order. As a result, execution of commands may be balanced between zones and lower latencies may be achieved overall for each zone. Improved performance or throughput of the storage device in handling zone commands may therefore result.
    Type: Application
    Filed: February 19, 2021
    Publication date: April 14, 2022
    Inventors: Dinesh Kumar Agarwal, Amit Sharma
  • Publication number: 20220113869
    Abstract: A storage system and method for time-duration-based efficient block management and memory access are provided. In one embodiment, a controller of the storage system is configured to receive time stamps from a host for each of a plurality of blocks in the memory; determine a time duration for programming each of the plurality of blocks based on the time stamps; and differentiate the plurality of blocks based on the time durations. Other embodiments are provided.
    Type: Application
    Filed: February 16, 2021
    Publication date: April 14, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventor: Dinesh Kumar Agarwal
  • Patent number: 11294579
    Abstract: Aspects of a multi-protocol storage device including a controller are provided which handle mode switches after a shutdown resulting in a large amount of unfinished work by phasing the work during and after initialization. The controller operates in a first mode such as an SD mode and a second mode such as a NVMe mode. In the event of a shutdown in the second mode resulting in unfinished work, the controller initializes in the first mode. During initialization, the controller determines whether a completion time for the unfinished work exceeds an initialization time in the first mode. When the completion time exceeds the initialization time, the controller performs a first portion of the work during initialization and postpones performance of at least a second portion of the unfinished work until after initialization. As a result, initialization timeouts in the first mode due to the unfinished work may be avoided.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: April 5, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ramanathan Muthiah, Hitesh Golechchha, Dinesh Kumar Agarwal
  • Patent number: 11281405
    Abstract: Aspects of a storage device including a plurality of dies and a controller are provided which allow for asymmetric die operation handling so that controller overheads associated with common resource intensive operations may be incurred in the background without delaying subsequent die operations. When the controller receives a command to perform an MLC operation such as programming a number of dies, the controller refrains from performing the MLC operation in one or more of the dies for a period of time while simultaneously performing the MLC operation in a remainder of the dies. Instead, the controller performs another operation, such as an SLC operation, another MLC operation, or a transfer operation, that involves a common resource in these dies during the period of time. Controller overheads associated with these other operations thus are incurred without creating bottlenecks when the number of dies is large, thereby improving storage device performance.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: March 22, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Amit Sharma, Abhinandan Venugopal, Dinesh Kumar Agarwal
  • Publication number: 20220086225
    Abstract: Storage devices and systems are capable of dynamically managing QoS requirements associated with host applications via a management interface. The management interface may the enable storage devices to: (i) decide which data needs to be transferred back to the hosts, (ii) choose to skip portions of the data transferred back to the hosts to improve throughput and maintain low cost, and (iii) operate contention resolutions with host applications. Furthermore, storage devices and systems may achieve a virtual throughput that may be greater than its actual physical throughput. The management interface may also be operated at an application level, which advantageously allows the devices and systems the capabilities of managing contention resolutions of host applications, and managing (changing, observing, fetching, etc.) one or more QoS requirements for each host application.
    Type: Application
    Filed: February 24, 2021
    Publication date: March 17, 2022
    Inventors: Dinesh Kumar Agarwal, Amit Sharma
  • Publication number: 20220083221
    Abstract: Data blocks may be optimized and managed in a mixed mode that utilizes a single-level cell (SLC) mode in combination with higher-density memory modes to promote full block utilization and to increase overall cycles of the data blocks. A data block cycling process in the mixed mode can place a data block in a higher-density memory mode that includes a multi-level cell (MLC) mode, a triple-level cell (TLC) mode, or a quad-level cell (QLC) mode, if the SLC cycle count of the data block is relatively higher as compared to other data blocks. Similarly, in the mixed mode, a data block may be placed in the SLC mode to store parity data or intermediate data if the corresponding TLC cycle count is relatively higher than other data blocks. Data clocks cycles may also be evenly distributed in the mixed mode, thereby balancing the mixed mode usage across all data blocks.
    Type: Application
    Filed: February 24, 2021
    Publication date: March 17, 2022
    Inventors: Dinesh Kumar Agarwal, Sourabh Sankule
  • Publication number: 20220076753
    Abstract: A storage system and method for a hybrid quad-level cell (QLC) write scheme for reduced random access memory (RAM) footprint and better performance are provided. In one example, a storage system includes a volatile memory and a non-volatile memory. A Foggy program operation is performed in a QLC memory in the non-volatile memory by writing two pages of data into the QLC memory. Then, a Fine program operation is performed in the QLC memory by reading the two pages of data written to the QLC memory in the Foggy program operation, reading two other pages of data from the volatile memory, and writing the two pages of data read from the QLC memory and the two other pages of data read from the volatile memory in the QLC memory.
    Type: Application
    Filed: February 22, 2021
    Publication date: March 10, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Sourabh Sankule, Dinesh Kumar Agarwal, Chetan Agrawal
  • Publication number: 20220075545
    Abstract: Storage devices are capable of identifying zones for sharing parity blocks across zones. Active zones may be segregated across multiple active zones having similar zone properties, and grouped so that parity buffers can be shared. By identifying zones for optimal parity sharing, storage devices and systems can: (i) maintain independent parity for all zones during initial zone writes (i.e. during an erased state when data is written directly to pages and not to the zones), (ii) track zone write pointers and frequency of writes in the zones, (iii) segregate zones with higher correlation and group them together, (iv) utilize these groupings placed across various channels so that zones with high correlations, comprising of the zones that are written together and at the same rate, share the parity buffers, and (v) load and XOR individual parity buffers for optimal parity sharing across all zones.
    Type: Application
    Filed: February 26, 2021
    Publication date: March 10, 2022
    Inventor: Dinesh Kumar Agarwal