Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

Abstract: One or more embodiments of a regulator circuit for providing power to a load device having a first power demand profile over time. The regulator circuit comprises a regulator and an energy storage device coupled to the regulator and the load device. The regulator circuit is configured to scavenge provided energy that is available beyond the first power demand profile. Further, the regulator circuit is configured to store that energy in the energy storage device, and the energy storage device is configured to augment deliverable peak power to the load device when the load device requires more power than is provided by the regulator circuit.

Abstract: A processor comprises a computational array of computational elements and an instruction dispatch circuit. The computational elements receive data operands via data lanes extending along a first dimension, and processes the operands based upon instructions received from the instruction dispatch circuit via instruction lanes extending along a second dimension. The instruction dispatch circuit receives raw instructions, and comprises an instruction dispatch unit (IDU) processor that processes a set of raw instructions to generate processed instructions for dispatch to the computational elements, where the number of processed instructions is not equal to the number of instructions of the set of raw instructions.

Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

Abstract: A processor comprises a computational array of computational elements and an instruction dispatch circuit. The computational elements receive data operands via data lanes extending along a first dimension, and processes the operands based upon instructions received from the instruction dispatch circuit via instruction lanes extending along a second dimension. The instruction dispatch circuit receives raw instructions, and comprises an instruction dispatch unit (IDU) processor that processes a set of raw instructions to generate processed instructions for dispatch to the computational elements, where the number of processed instructions is not equal to the number of instructions of the set of raw instructions.

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: A deterministic apparatus comprising a deterministic near-compute memory communicatively coupled with and proximate to a deterministic processor. The deterministic near-compute memory comprises a plurality of data banks having a global memory address space, a control bus, a data input bus and a data output bus for each data bank. The deterministic processor is configured to initiate, via the control bus, retrieval of a set of data from the plurality of data banks. The retrieved set of data comprises at least one row of a selected one of the data banks passed via the data output bus onto a plurality of stream registers of the deterministic processor.

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

Abstract: The present disclosure provides circuits and methods that can be used to update configurations. An example circuit can include a plurality hLUTs and a plurality of registers configured to propagate a set of data or a portion thereof to the plurality of hLUTs. An hLUT of the plurality of hLUTs can have a transformation unit comprising transformation circuitry configured to (i) receive the set of data or the portion thereof from a register of the plurality of registers and (ii) transform the set of data or the portion thereof into configurations for the hLUT.

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

Abstract: A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.