Patents by Inventor Ding Wang

Ding Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240222215
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.
    Type: Application
    Filed: March 14, 2024
    Publication date: July 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 12010556
    Abstract: This application relates to a network device transmission bandwidth reduction method and related device for reducing a transmission bandwidth of a network device, thereby reducing power consumption and battery life of terminal devices. In one embodiment, a terminal receives transmission bandwidth reduction configuration information sent by a network device, where the transmission bandwidth reduction configuration information includes a set of transmission bandwidth reduction parameters supported by the network device. In response, the terminal sends a target transmission bandwidth reduction coefficient to the network device, where the target transmission bandwidth reduction coefficient is a transmission bandwidth reduction coefficient of a serving cell expected by the terminal. A serving cell is one or more cells that currently provide services for the terminal.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: June 11, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ding Wang, Liwei Cui, Jian Wang, Haibo Xu
  • Publication number: 20240166533
    Abstract: A high-nickel ternary core-shell precursor for a lithium battery, a positive electrode material and a preparation method therefor. The chemical structural formula of the precursor is zNi(C4H7N2O2)2—Nix-zM1yM21-x-y(OH)2, wherein M1 and M2 are two of cobalt, aluminum, and manganese. The preparation method comprises: pumping a prepared metal salt solution, a dimethylglyoxime-ammonia water composite solution, and an ammonia water solution into a reaction kettle, maintaining the pH of a reaction system, and controlling the reaction time to obtain a sphere-like precursor inner core with a structural formula of Ni(C4H7N2O2)2; pumping the metal salt solution and the ammonia water solution, stopping pumping the dimethylglyoxime-ammonia water composite solution, pumping a sodium hydroxide solution to obtain a sphere-like core-shell precursor, washing, drying, sieving and deironing the precursor, mixing with a lithium source, and calcining to prepare the positive electrode material.
    Type: Application
    Filed: August 18, 2022
    Publication date: May 23, 2024
    Applicant: JINGMEN GEM CO., LTD.
    Inventors: Kaihua XU, Kun ZHANG, Dongming JIA, Cong LI, Xing YANG, Xiaofei XUE, Liangjiao FAN, Xiaofei CHEN, Xueqian LI, Xiaoshuai ZHU, Hao LV, Wenfang YUAN, Ding WANG, Xianjin YUE
  • Publication number: 20240160225
    Abstract: A control method includes generating, through a processor, route data of a route, instructing the movable object to execute the route data, detecting an execution status of the movable object, in response to detecting that the movable object is in a route recovery state, controlling the movable object in the route recovery state to resume the execution of the route according to a starting position. The starting position includes at least one of a waypoint of the plurality of waypoints before an interruption, a position determined according to a flight position recorded at a time of the interruption, or a user-designated waypoint.
    Type: Application
    Filed: December 18, 2023
    Publication date: May 16, 2024
    Inventors: Zhuo GUO, Zhuo XIE, Haoyu LI, Wenlin LI, Ding WANG, Zebo YANG
  • Patent number: 11976058
    Abstract: The present disclosure relates generally to aromatic derivatives that are inhibitors of FGFR4 and are useful in treating FGFR4-associated diseases or conditions. Compositions containing the compounds of the present disclosure are also provided.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: May 7, 2024
    Assignee: BIOARDIS LLC
    Inventors: Ding Wang, Ning Shao, Hongbin Yuan, Frank Kayser
  • Publication number: 20240128232
    Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ding Wang, Yen-Fu Su, Hao-Cheng Hou, Jung-Wei Cheng, Chien-Hsun Lee, Hsin-Yu Pan
  • Patent number: 11961777
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao
  • Publication number: 20240105631
    Abstract: Embodiments provide a method of performing a carrier switch for a device wafer, attaching a second wafer and removing a first wafer. A buffer layer is deposited over the device wafer, buffer layer reducing the topography of the surface of the device wafer. After the carrier switch a film-on-wire layer is removed from the buffer layer and then the buffer layer is at least in part removed.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 28, 2024
    Inventors: Jeng-An Wang, Sheng-Chi Lin, Hao-Cheng Hou, Tsung-Ding Wang, Chien-Hsun Lee
  • Publication number: 20240071999
    Abstract: A first polymer layer is formed across a package region and a test region. A first metal pattern is formed in the package region and a first test pattern is simultaneously formed in the test region. The first metal pattern has an upper portion located on the first polymer layer and a lower portion penetrating through the first polymer layer, and the first test pattern is located on the first polymer layer and has a first opening exposing the first polymer layer. A second polymer layer is formed on the first metal pattern in the package region and a second test pattern is simultaneously formed on the first test pattern in the test region. The second polymer layer has a second opening exposing the upper portion of the first metal pattern, and the second test pattern has a third opening greater than the first opening of the first test pattern.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tseng Hsing Lin, Chien-Hsun Lee, Tsung-Ding Wang, Jung-Wei Cheng, Hao-Cheng Hou, Sheng-Chi Lin, Jeng-An Wang, Yao-Cheng Wu
  • Publication number: 20240071939
    Abstract: A semiconductor structure includes a composite redistribution structure, a first interconnect device and an integrated circuit (IC) package component. The composite redistribution structure includes a first redistribution structure, a second redistribution structure and a third redistribution structure. The second redistribution structure is located between the first redistribution structure and the third redistribution structure. The first interconnect device is embedded in the second redistribution structure. The first interconnect device includes a plurality of metal connectors leveled with a surface of the second redistribution structure and electrically connected to the third redistribution structure. The IC package component is disposed over the third redistribution structure and electrically connected to the first interconnect device via the third redistribution structure.
    Type: Application
    Filed: August 28, 2022
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Wei Cheng, Tsung-Ding Wang, Yu-Min Liang, Hao-Cheng Hou
  • Publication number: 20240061037
    Abstract: A package structure includes a substrate component, a redistribution structure, a package structure, and a probe head. The substrate component is laterally covered by an insulating encapsulation. The redistribution structure is disposed over the substrate component and the insulating encapsulation and electrically connected with the substrate component at a first side, wherein the redistribution structure comprises: a dielectric layer at a second side opposite to the first side; at least one conductive pad disposed in the dielectric layer, wherein a portion of the at least one conductive pad is exposed by the dielectric layer; and at least one conductive pattern in contact with the portion of the at least one conductive pad, wherein a hardness of the at least one conductive pattern is greater than a hardness of the at least one conductive pad. The probe head is electrically connected with the at least one conductive pattern and the at least one conductive pad.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 22, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Cheng Hou, Jung-Wei Cheng, Tsung-Ding Wang, Chien-Hsun Lee
  • Patent number: 11910348
    Abstract: A registration method applied in a terminal device includes sending a first request, where the first request is used to request to register in a first cell, receiving a first message, where the first message is used to indicate that the terminal device is successfully registered in the first cell, when the first message does not carry a first network slice identifier and the terminal device cannot establish a protocol data unit (PDU) session on a first network slice corresponding to the first network slice identifier, sending a second request, where the second request is used to request to register in a second cell, receiving a second message, where the second message carries a second network slice identifier, and establishing the PDU session on a second network slice corresponding to the second network slice identifier.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: February 20, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ding Wang, Xiaoyan Duan, Liwei Cui
  • Publication number: 20240055468
    Abstract: A method of forming an inductor including forming a first redistribution structure on a substrate, forming a first conductive via over and electrically connected to the first redistribution structure, depositing a first magnetic material over a top surface and sidewalls of the first conductive via, coupling a first die and a second die to the first redistribution structure, encapsulating the first die, the second die, and the first conductive via in an encapsulant, and planarizing the encapsulant and the first magnetic material to expose the top surface of the first conductive via while a remaining portion of the first magnetic material remains on sidewalls of the first conductive via, where the first conductive via and the remaining portion of the first magnetic material provide an inductor.
    Type: Application
    Filed: January 23, 2023
    Publication date: February 15, 2024
    Inventors: Wei-Yu Chen, Chung-Hui Chen, Hao-Cheng Hou, Jung Wei Cheng, Tsung-Ding Wang, Chien-Hsun Lee, Shang-Yun Hou
  • Publication number: 20240047509
    Abstract: A method includes forming an inductor die, which includes forming a metal via over a substrate, forming a magnetic shell encircling the metal via, with the metal via and the magnetic shell collectively forming an inductor, and depositing a dielectric layer around the magnetic shell. The method further includes placing the inductor die over a carrier, encapsulating the inductor die in an encapsulant, forming redistribution lines electrically connecting to the inductor, and bonding a device die to the redistribution lines. The device die is electrically coupled to the inductor through the redistribution lines.
    Type: Application
    Filed: January 5, 2023
    Publication date: February 8, 2024
    Inventors: Hao-Cheng Hou, Tsung-Ding Wang, Jung Wei Cheng, Chien-Hsun Lee, Shang-Yun Hou
  • Publication number: 20240047322
    Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes an integrated substrate and a package component. The integrated substrate includes a substrate component laterally covered by an insulating encapsulation, a redistribution structure disposed over the substrate component and the insulating encapsulation, first conductive joints coupling the redistribution structure to the substrate component, and a buffer layer disposed on a lowermost dielectric layer of the redistribution structure and extending downwardly to cover an upper portion of each of the first conductive joints. A lower portion of each of the first conductive joints connected to the upper portion is covered by the insulating encapsulation. The package component disposed over and electrically coupled to the redistribution structure includes a semiconductor die laterally covered by an encapsulant.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Liang Chen, Chi-Yang Yu, Yu-Min Liang, Hao-Cheng Hou, Jung-Wei Cheng, Tsung-Ding Wang
  • Patent number: 11894341
    Abstract: A semiconductor package includes a semiconductor die, an encapsulant, a first and second dielectric layer, a through via, an extension pad, and a routing via. The semiconductor die includes a contact post. The first dielectric layer extends on the encapsulant. The through via extends through the first dielectric layer and has one end contacting the contact post. The extension pad is disposed on the first dielectric layer, contacting an opposite end of the through via with respect to the contact post. The extension pad has an elongated shape, a first end of the extension pad overlaps with the contact post and the through via, and a second end of the extension pad overlaps with the encapsulant. The second dielectric layer is disposed on the first dielectric layer and the extension pad. The routing via extends through the second dielectric layer to contact the second end of the extension pad.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ding Wang, Yen-Fu Su, Hao-Cheng Hou, Jung-Wei Cheng, Chien-Hsun Lee, Hsin-Yu Pan
  • Publication number: 20240038646
    Abstract: Semiconductor device packages and methods of forming the same are discussed. In an embodiment, a device includes: a redistribution structure comprising an upper dielectric layer and an under-bump metallization; a buffer feature on the under-bump metallization and the upper dielectric layer, the buffer feature covering an edge of the under-bump metallization, the buffer feature bonded to the upper dielectric layer; a reflowable connector extending through the buffer feature, the reflowable connector coupled to the under-bump metallization; an interposer coupled to the reflowable connector; and an encapsulant around the interposer and the reflowable connector, the encapsulant different from the buffer feature.
    Type: Application
    Filed: August 1, 2022
    Publication date: February 1, 2024
    Inventors: Chi-Yang Yu, Chin-Liang Chen, Hao-Cheng Hou, Jung Wei Cheng, Yu-Min Liang, Tsung-Ding Wang
  • Patent number: 11886203
    Abstract: A flight control method includes displaying a user interface configured to receive an operation instruction including coordinates of waypoints, generating route data of a route based on the coordinates of the waypoints, sending the route data to an aircraft to instruct the aircraft to execute the route, recording an interruption point during execution of the route by the aircraft, displaying a plurality of candidate starting points including at least one of the interruption point, a last waypoint of the route before the interruption point, a next waypoint of the route after the interruption point, or a user-designated waypoint, in response to a selection instruction, selecting a target starting point from the plurality of candidate starting points, and controlling the aircraft in an interrupted state to fly to the target starting point and resume the execution of the route from the target starting point.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: January 30, 2024
    Assignee: SZ DJI TECHNOLOGY CO., LTD.
    Inventors: Zhuo Guo, Zhuo Xie, Haoyu Li, Wenlin Li, Ding Wang, Zebo Yang
  • Publication number: 20240030157
    Abstract: A semiconductor package provided herein includes a package substrate and a semiconductor device. The package substrate includes a redistribution structure, an interconnect structure bonded to the interconnect structure and an insulation material laterally surrounding the interconnect structure, wherein the redistribution structure has a reduced structure and the insulation material fills the reduced structure. The semiconductor device is bonded to the package substrate. In addition, a method of fabricating a semiconductor package is also provided and includes a precut process forming the reduced structure in the redistribution structure of the package substrate.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Liang Chen, Hao-Cheng Hou, Yu-Min Liang, Jung-Wei Cheng, Tsung-Ding Wang
  • Publication number: 20230358786
    Abstract: A substrate structure includes a core substrate, a redistribution layer, a plurality of test pads, a first protective coating, at least one conductive pad and a passive device. The redistribution layer is disposed on and electrically connected to the core substrate. The test pads are disposed over the redistribution layer. The first protective coating is coated on the test pads. The conductive pad is d disposed on the redistribution layer aside the plurality of test pads. The passive device is disposed on and electrically connected to the at least one conductive pad.
    Type: Application
    Filed: May 6, 2022
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Yu-Min Liang, Hao-Cheng Hou, Tsung-Ding Wang, Chien-Hsun Lee, Chung-Shi Liu, Jung-Wei Cheng