Abstract: Disclosed are a compound represented by the general Formula (I), or a stereisomer, tautomer, derivative, prodrug or pharmaceutically acceptable salt thereof, and a method for preparing the compound and use of the compound in manufacture of a medicament for treating a neuropathic pain and/or neuropathic pain syndrome or a medicament for combating an inflammation: wherein R1 is selected from hydrogen, halogen, alkyl, cyano and haloalkyl, R2 and R3 are independently selected from hydrogen, halogen, alkyl, haloalkyl and nitro, and R1, R2 and R3 are not hydrogen at the same time; furthermore, when either R2 or R3 is nitro or halogen, the other two of R1, R2 and R3 are not hydrogen at the same time. The compound has good effects in treating a neuropathic pain and/or neuropathic pain syndrome and good effects in combating an inflammation, and has not side effects such as addiction.

Abstract: A laminated structure and the manufacturing methods thereof are provided. The structure includes an interconnect substrate having a first surface and a second surface opposite to the first surface, an insulating encapsulant laterally wrapping the interconnect substrate, and a redistribution structure disposed on the first surface of the interconnect substrate and electrically connected with the interconnect substrate. The redistribution structure has a third surface facing the first surface and a fourth surface opposite to the third surface. The redistribution structure includes first pads, second pads located beside the first pads, and protective patterns disposed on the first pads and covering the first pads. The first pads include pad portions protruded from the fourth surface and the protective patterns are in contact with sidewalls and top surfaces of the pad portions of the first pads.

Abstract: A method includes forming a build-up package substrate, which includes forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs, forming a first plurality of through-vias on the first plurality of RDLs, bonding an interconnect die to the second plurality of RDLs, encapsulating the interconnect die and the first plurality of through-vias in a first encapsulant, and forming a third plurality of RDLs over the first encapsulant. The third plurality of RDLs are electrically connected to the first plurality of through-vias. An organic package substrate is bonded to the build-up package substrate. The build-up package substrate and the organic package substrate in combination form a compound organic package substrate. A first package component and a second package component are bonded to the compound organic package substrate, and are electrically interconnected through the interconnect die.

Abstract: A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.

Abstract: A method includes forming a composite package substrate. The formation of the composite package substrate includes encapsulating an interconnect die in an encapsulant, with the interconnect die including a plurality of through-vias therein, and forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs on opposite sides of the interconnect die. The method further includes bonding an organic package substrate to the composite package substrate, and bonding a first package component and a second package component to the first plurality of RDLs. The first package component and the second package component are electrically interconnected through the interconnect die and the first plurality of RDLs.

Abstract: An assembly including at least one semiconductor die and an interposer is provided. A packaging substrate including substrate bonding pads is provided. The packaging substrate includes a first horizontal surface facing the assembly, a second horizontal surface located on an opposite side of the first horizontal surface, and an opening extending between the first horizontal surface and the second horizontal surface. The assembly is attached to the packaging substrate by bonding first solder material portions bonded to a respective one of the substrate bonding pads and to a respective one of first interposer bonding pads located on the interposer.

Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

Abstract: A connector is disclosed that includes a housing and first and second attachment areas located in the housing and spaced apart from each other along the mating direction of the connector. The second, but not the first, attachment area is designed to move relative to the housing. The connector further includes an optical waveguide that is permanently attached to, and under a first bending force between, the first and second attachment areas. The connector also includes a light coupling unit located in the housing for receiving light from the optical waveguide and transmitting the received light to a mating connector along a direction different than the mating direction of the connector. The mating of the connector to the mating connector causes the optical waveguide to be under a greater second bending force between the first and second attachment areas.

Abstract: A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.

Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

Abstract: A thermochromic polymer composition including a base polymer material; a temperature sensitive material, which changes a color of the thermochromic polymer composition in response to a temperature change; and a stabilizer, which enhances stability performance of the thermochromic polymer composition. The thermochromic polymer composition which has a good thermochromic performance and good thermal performance and thus could provide a visible indication of the overheat condition. An electrical device is formed from the thermochromic polymer composition. A further embodiment of the process for preparing the thermochromic polymer composition and forming the electrical device.

Abstract: A nitride semiconductor substrate (11, 21) includes: a substrate (2); and an AlN-containing film (100, 200) provided above the substrate (2). A thickness of the AlN-containing film (100, 200) is at most 10000 nm, and a threading dislocation density of the AlN-containing film (100, 200) is at most 2×108 cm?2.

Abstract: A method of fabricating a heterostructure includes providing a substrate, and implementing a non-sputtered, epitaxial growth procedure at a growth temperature to form a wurtzite structure supported by the substrate. The wurtzite structure includes an alloy of gallium nitride. The non-sputtered, epitaxial growth procedure is configured to incorporate a group IIIB element into the alloy. The wurtzite structure exhibits a breakdown field strength greater than a ferroelectric coercive field strength of the wurtzite structure.

Abstract: This application provides a terminal device and a communication method. The terminal device is in a dual-connectivity network including a long term evolution (LTE) link and a new radio (NR) link, and when the terminal device detects that the terminal device is in a power saving mode, and/or when the terminal device detects that battery power of the terminal device is less than or equal to a first preset value, and/or when the terminal device detects that temperature of a rear cover of the terminal device is greater than or equal to a second preset value, the terminal device releases the NR link, and uses the LTE link for communication.

Abstract: A semiconductor package is provided. The semiconductor package includes: semiconductor dies, separated from one another, and including die I/Os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die I/Os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die I/Os and rout the die I/Os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region.

Abstract: The invention relates to a composition for the immediate termination of a free-radical polymerization, the use thereof for the stabilization of free-radically polymerizable monomers against free-radical polymerization and a method for the immediate termination of free-radical polymerizations.

Abstract: A semiconductor package includes a first semiconductor die, a molded die, a third encapsulant, and a redistribution structure. The molded die includes a chip, a first encapsulant, and a second encapsulant. The first encapsulant laterally wraps the chip. The second encapsulant laterally wraps the first encapsulant. The third encapsulant laterally wraps the first semiconductor die and the molded die. The redistribution structure extends on the second encapsulant, the third encapsulant, and the first semiconductor die. The redistribution structure is electrically connected to the first semiconductor die and the molded die. The second encapsulant separates the first encapsulant from the third encapsulant.

Abstract: A method of forming a semiconductor structure includes the following operations. A first conductive structure is formed on a first side of a first glass carrier. A second glass carrier is bonded to the first conductive structure. Conductive vias are formed to penetrate through the first glass carrier, and the conductive vias are electrically connected to the first conductive structure. A second conductive structure is formed on a second side of the first glass carrier opposite to the first side, and the second conductive structure is electrically connected to the conductive vias.

Abstract: A semiconductor package includes a first integrated circuit, a first conductive via, a second conductive via, a second integrated circuit, a third conductive via and an encapsulant. The first conductive via is disposed in a first passivation layer over the first integrated circuit. The second conductive via is disposed in a second passivation layer over the first passivation layer. The second conductive via is electrically connected to the first conductive via. The third conductive via is disposed over the second integrated circuit, wherein a surface of the third conductive via is substantially coplanar with a surface of the third conductive via. The encapsulant encapsulates the first integrated circuit, the first passivation layer, the second passivation layer, the second integrated circuit and the third conductive via.