Abstract: Embodiments of the disclosure relate to a three-dimensional (3D) inductor-capacitor (LC) circuit. The 3D LC circuit includes an inductor formed by a conductive ribbon of a defined height and a conductive sleeve conductively coupled to the conductive ribbon. The conductive sleeve and the conductive ribbon can generate a built-in capacitance(s) for the 3D LC circuit. In examples discussed herein, the conductive ribbon can also help reduce the skin effect of the inductor by distributing an electrical current across the defined height of the conductive ribbon. By generating the built-in capacitance(s) and distributing the electrical current across the defined height of the conductive ribbon, it is possible to reduce current crowding and improve quality factor (Q-factor) of the 3D LC circuit. As a result, it is possible to couple one or more 3D LC circuits to form a high performance radio frequency (RF) filter(s) for the fifth-generation (5G) wireless communication systems.

Abstract: A semiconductor die including a substrate, a device layer over the substrate, and an adjustable component in the device layer is provided, where a surface of the device layer opposite the substrate is the frontside of the semiconductor die. At least a portion of the substrate is removed to expose a backside of the semiconductor die opposite the frontside. The adjustable component is then trimmed through the backside of the semiconductor die.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.

Abstract: Dynamic error vector magnitude (EVM) compensation is accomplished for radio frequency (RF) power amplifiers (PAs) which experience EVM distortion from thermal settling. Thermal settling causes gain changes in the PAs, and systems, apparatuses, and methods of the present disclosure compensate for known thermal transients of PAs.

Abstract: RF PA circuitry includes an RF signal path, an adjustable component, a distortion compensation feedback loop including distortion compensation circuitry, RF noise filtering circuitry, and baseband noise filtering circuitry. The adjustable component is located in the RF signal path. The distortion compensation feedback loop is coupled in parallel with at least a portion of the RF signal path, and includes the distortion compensation circuitry. Further, the distortion compensation circuitry is configured to adjust one or more parameters of the adjustable component via a component adjustment signal based on a measurement of a signal at an output of the RF signal path. The RF noise filtering circuitry is coupled in the RF signal path and configured to attenuate noise therein. The baseband noise filtering circuitry is coupled between the distortion compensation circuitry and the adjustable component and configured to attenuate noise in the component adjustment signal.

Abstract: A multi radio access technology (RAT) circuit is provided. The multi RAT power management circuit can concurrently support multiple different RATs using a single power management integrated circuit and a single power amplifier. The multi RAT power management circuit receives a first digital signal modulated based on a first RAT and a second digital signal modulated based on a second RAT. Control circuitry generates a composite output signal, which includes the first digital signal and the second digital signal and corresponds to a time-variant composite signal envelope derived from a respective peak envelope of the first and the second digital signals. The control circuitry generates a voltage control signal having a time-variant target voltage envelope tracking the time-variant composite signal envelope of the composite output signal. As such, the multi RAT power management circuit can concurrently support the multiple different RATs without increasing size, costs, complexity, and/or power consumption.

Abstract: Embodiments of an acoustic wave filter system that includes at least one acoustic wave filter and acoustic wave tuning control circuitry are disclosed. The acoustic wave filter includes at least one acoustic wave resonator and defines a passband. To provide tuning for calibration or for dynamic filter operation, the acoustic wave tuning control circuitry is configured to bias one or more of the acoustic wave resonators with bias voltages. Biasing an acoustic wave resonator affects the resonances of the resonator, thereby allowing for the passband of the acoustic wave resonator to be tuned. Accordingly, the acoustic wave tuning control circuitry is configured to adjust the bias voltages so that the acoustic wave filter shifts the passband. In this manner, the passband of the acoustic wave filter can be tuned with high degree of accuracy and without requiring physical alterations to the acoustic wave resonators.

Abstract: LNA circuitry includes an input node, and output node, a primary amplifier stage, a first ancillary amplifier stage, and an input gain selection switch. The primary amplifier stage is configured to provide a first gain response between a primary amplifier stage input node and a primary amplifier stage output node, wherein the primary amplifier stage input node is coupled to the input node and the primary amplifier stage output node is coupled to the output node. The first ancillary amplifier stage is configured to provide a second gain response between a first ancillary amplifier stage input node and a first ancillary amplifier stage output node, wherein the first ancillary amplifier stage output node is coupled to the primary amplifier stage output node. The input gain selection switch is coupled between the input node and the first ancillary amplifier stage input node.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned integrated passive die (IPD) attached to the printed circuit substrate. A protective layer is disposed over the thinned IPD to protect passive devices integrated within the thinned IPD, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 103 Ohm-cm.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.

Abstract: An amplifier having improved linearity is disclosed. The amplifier includes a main transistor having a first current input terminal, a first current output terminal, and a first control terminal coupled to an RF input terminal that receives a signal voltage. A cascode transistor has a second current input terminal coupled to an RF output terminal for outputting an amplified signal. The cascode transistor has a second control terminal, and a second current output terminal coupled to the first current input terminal. Linearization circuitry has a bias output terminal coupled to the second control terminal. The linearization circuitry is configured to generate a bias signal at the bias output terminal to maintain a quiescent point of the main transistor for a given load coupled to the RF output terminal such that output conductance of the main transistor decreases nonlinearly with increasing main voltage and increases nonlinearly with decreasing main voltage.

Abstract: An electronic component made up of field-effect transistor (FET) cells is disclosed. Each FET cell includes a finger region having drain, gate, and source fingers disposed over a semiconductor substrate. An isolation region extends across a first end of the finger region. An off-state linearization region abuts the first end of the isolation region. A doped well is disposed within the off-state linearization region over the semiconductor substrate. A dielectric layer is disposed over the doped region. A first conductive stripe is disposed over the dielectric layer in longitudinal alignment with the drain finger. A second conductive stripe is disposed over the dielectric layer in longitudinal alignment with the drain finger. A drain finger electrode is aligned over and coupled to both the drain finger and the first conductive stripe. A source finger electrode is aligned over and coupled to both the source finger and the second conductive stripe.

Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned integrated passive die (IPD) attached to the printed circuit substrate. A protective layer is disposed over the thinned IPD to protect passive devices integrated within the thinned IPD, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 103 Ohm-cm.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.

Abstract: Circuitry that includes a radio frequency (RF) power amplifier (PA) and a dynamic supply boosting circuit, is disclosed. The RF PA receives and amplifies an RF input signal to provide an RF transmit signal using a PA power supply voltage. The dynamic supply boosting circuit provides the PA power supply voltage using a dynamic supply input voltage, wherein when a peak-to-average (PAR) of the RF input signal exceeds a PAR threshold, the dynamic supply boosting circuit boosts the PA power supply voltage, such that the PA power supply voltage is greater than the dynamic supply input voltage.

Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.

Abstract: RF communications circuitry, which includes a first tunable RF filter and a first RF low noise amplifier (LNA) is disclosed. The first tunable RF filter includes a pair of weakly coupled resonators, and receives and filters a first upstream RF signal to provide a first filtered RF signal. The first RF LNA is coupled to the first tunable RF filter, and receives and amplifies an RF input signal to provide an RF output signal.

Abstract: An apparatus including a main transistor-based switch having a first end node and a second end node and an ON-state linearization network that is coupled between the first end node and the second end node of the main transistor-based switch is disclosed. The ON-state linearization network is configured to receive a monitored signal that corresponds to a signal across the first end node and the second end node and cancel at least a portion of non-linear distortion generated by the main transistor-based switch when the main transistor-based switch is in an ON-state based on the monitored signal. A control signal applied to a control input of the ON-state linearization network causes the ON-state linearization network to activate when the main transistor-based switch is in the ON-state and to deactivate the ON-state linearization network when the main transistor-based switch is an OFF-state.