Abstract: The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.

Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die is an integrated passive die (IPD) without a silicon substrate layer. A protective layer is disposed over the IPD, wherein the protective layer has a thermal conductivity between 2 watts per meter Kelvin (W/mK) and 6600 W/mK and an electrical resistivity of greater than 106 Ohm-cm.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.

Abstract: Disclosed is a radio frequency (RF) switch that includes a substrate and a plurality of elongated drain/source (D/S) diffusion regions laterally disposed in parallel with one another and separated by a plurality of elongated channel regions. A plurality of elongated D/S resistor regions extends between an adjacent pair of plurality of elongated D/S diffusion regions, and a plurality of elongated gate structures resides over corresponding ones of the elongated channel regions. A silicide layer resides over a majority of at least top surfaces of the plurality of the elongated D/S diffusion regions and the plurality of elongated gate structures, wherein less than a majority of each of the plurality of the elongated D/S resistor regions are covered by the silicide layer.

Abstract: The present disclosure relates to a microelectronics package with an inductive element and a magnetically enhanced mold compound component, and a process for making the same. The disclosed microelectronics package includes a module substrate, a thinned flip-chip die with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, the magnetically enhanced mold compound component, and a mold compound component. The thinned flip-chip die is attached to the module substrate and includes a device layer with an inductive element embedded therein. Herein, the inductive element is underlying the first surface portion and not underlying the second surface portion. The magnetically enhanced mold compound component is formed over the first surface portion. The mold compound component is formed over the second surface portion, not over the first surface portion, and surrounding the magnetically enhanced mold compound component.

Abstract: This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the same. In one method, a printed circuit board is provided with semiconductor die. The semiconductor die includes a Back-End-of-Line (BEOL) region, a Front-End-of-Line (FEOL) region, and a semiconductor handle such that the BEOL region, the FEOL region, and the semiconductor handle are stacked. A first polymer layer is provided over the printed circuit board so as to cover the semiconductor die. The semiconductor handle of the semiconductor die is exposed through the first polymer layer and removed. A second polymer layer is then provided so that the BEOL region, the FEOL region, and at least a portion of the second polymer layer are stacked. The second polymer layer may be provided to have high thermal conductivity and electric isolation properties thereby providing advantageous package characteristics.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a non-silicon thermal conductive component, a silicon layer with a thickness between 100 ? and 10 ?m over the thermal conductive component, a buried oxide (BOX) layer over the silicon layer, an epitaxial layer over the BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the silicon layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

Abstract: The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.

Abstract: Radio frequency (RF) filters configured to filter undesired signal components (e.g., noise and harmonics) from RF signals are disclosed. In one embodiment, an RF filter includes a first inductor coil having a first winding and a second inductor coil having a second winding and a third winding. The second winding of the second inductor coil is configured to have a first mutual magnetic coupling with the first winding, while the third winding of the second inductor coil is configured to have a second mutual magnetic coupling with the first winding. The second winding is connected to the third winding such that the first mutual magnetic coupling and the second mutual magnetic coupling are in opposition. In this manner, the first inductor coil and the second inductor coil may be provided in a compact arrangement while providing weak mutual magnetic coupling between the first inductor coil and the second inductor coil.

Abstract: Embodiments of an apparatus are disclosed that includes a first three dimensional (3D) inductor and a second 3D inductor. The first three dimensional (3D) inductor has a first conductive path shaped as a first two dimensional (2D) lobe laid over a first 3D volume. In addition, the second 3D inductor has a second conductive path, wherein the second 3D inductor is inserted into the first 3D inductor so that the second conductive path at least partially extends through the first 3D volume. Since second 3D inductor is inserted into the first 3D inductor, the 3D inductors may be coupled to one another. Depending on orientation and distances of structures provided by the 3D inductors, the 3D inductors may be weakly or moderately coupled.

Abstract: The present disclosure relates to a microelectronics package with an inductive element and a magnetically enhanced mold compound component, and a process for making the same. The disclosed microelectronics package includes a module substrate, a thinned flip-chip die with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, the magnetically enhanced mold compound component, and a mold compound component. The thinned flip-chip die is attached to the module substrate and includes a device layer with an inductive element embedded therein. Herein, the inductive element is underlying the first surface portion and not underlying the second surface portion. The magnetically enhanced mold compound component is formed over the first surface portion. The mold compound component is formed over the second surface portion, not over the first surface portion, and surrounding the magnetically enhanced mold compound component.

Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.

Abstract: Antenna aperture tuning circuitry includes a first signal path and a second signal path coupled in parallel between an antenna radiating element and ground. A first LC resonator and a second LC resonator are each coupled between the first signal path and ground. The first LC resonator and the second LC resonator are electromagnetically coupled such that a coupling factor between the first LC resonator and the second LC resonator is between about 1.0% and 40.0%. A third LC resonator and a fourth LC resonator are each coupled between the second signal path and ground. The third LC resonator and the fourth LC resonator are electromagnetically coupled such that a coupling factor between the third LC resonator and the fourth LC resonator is between about 1.0% and 40.0%.

Abstract: Circuitry that includes a radio frequency (RF) power amplifier (PA) and a dynamic supply boosting circuit, is disclosed. The RF PA receives and amplifies an RF input signal to provide an RF transmit signal using a PA power supply voltage. The dynamic supply boosting circuit provides the PA power supply voltage using a dynamic supply input voltage, wherein when a peak-to-average (PAR) of the RF input signal exceeds a PAR threshold, the dynamic supply boosting circuit boosts the PA power supply voltage, such that the PA power supply voltage is greater than the dynamic supply input voltage.

Abstract: The present disclosure relates to a microelectronics package with an inductive element and a magnetically enhanced mold compound component, and a process for making the same. The disclosed microelectronics package includes a module substrate, a thinned flip-chip die with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, the magnetically enhanced mold compound component, and a mold compound component. The thinned flip-chip die is attached to the module substrate and includes a device layer with an inductive element embedded therein. Herein, the inductive element is underlying the first surface portion and not underlying the second surface portion. The magnetically enhanced mold compound component is formed over the first surface portion. The mold compound component is formed over the second surface portion, not over the first surface portion, and surrounding the magnetically enhanced mold compound component.

Abstract: This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the same. In one method, a printed circuit board is provided with semiconductor die. The semiconductor die includes a Back-End-of-Line (BEOL) region, a Front-End-of-Line (FEOL) region, and a semiconductor handle such that the BEOL region, the FEOL region, and the semiconductor handle are stacked. A first polymer layer is provided over the printed circuit board so as to cover the semiconductor die. The semiconductor handle of the semiconductor die is exposed through the first polymer layer and removed. A second polymer layer is then provided so that the BEOL region, the FEOL region, and at least a portion of the second polymer layer are stacked. The second polymer layer may be provided to have high thermal conductivity and electric isolation properties thereby providing advantageous package characteristics.

Abstract: A Radio Frequency (RF) switch having two or more stages coupled in series is disclosed. A first Field-Effect Transistor (FET) with a first control terminal is coupled across a gate resistor to shunt the gate resistor when the first FET is on. An RF switching device is configured to pass an RF signal between a signal input and a signal output when the RF switching device is on. A second FET having a second control terminal coupled to an acceleration output is configured to shunt the RF switching device when the second FET is on. A third FET is coupled between the first control terminal and the signal input for controlling charge on a gate of the first FET. A third control terminal of the third FET is coupled to an acceleration input for controlling an on/off state of the third FET.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a non-silicon thermal conductive component, a silicon layer with a thickness between 100 ? and 10 ?m over the thermal conductive component, a buried oxide (BOX) layer over the silicon layer, an epitaxial layer over the BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the silicon layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.

Abstract: This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the same. In one method, a printed circuit board is provided with semiconductor die. The semiconductor die includes a Back-End-of-Line (BEOL) region, a Front-End-of-Line (FEOL) region, and a semiconductor handle such that the BEOL region, the FEOL region, and the semiconductor handle are stacked. A first polymer layer is provided over the printed circuit board so as to cover the semiconductor die. The semiconductor handle of the semiconductor die is exposed through the first polymer layer and removed. A second polymer layer is then provided so that the BEOL region, the FEOL region, and at least a portion of the second polymer layer are stacked. The second polymer layer may be provided to have high thermal conductivity and electric isolation properties thereby providing advantageous package characteristics.