Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

Abstract: A non-volatile memory cell array, comprising sector selection transistors controlled by a voltage applied to sector selection lines, first through fourth memory cells connected in series to the sector selection transistors, a first common source line connected between the first memory cell and the second memory cell, and a second common source line connected between the third memory cell and the fourth memory cell and separated from the first common source line. A first voltage is applied to the first common source line, and a second voltage different from the first voltage is applied to the second common source line.

Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

Abstract: A damper including a cylinder, a piston inserted in the cylinder, a movable member disposed in the piston to be movable in the cylinder in a length direction of the cylinder, and a weight sensor mounted on an inner surface of the cylinder, facing an end of the piston, to perceive weight loaded on the piston through contact with the movable member. When applied to a washing machine, the damper is capable of perceiving accurate weight of the laundry supplied in the washing machine.

Abstract: Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

Abstract: A semiconductor device includes an active region in a substrate, first to third gate structures crossing the active region and sequentially arranged parallel to each other, a first doped region in the active region between the first and second gate structures and having a first horizontal width and a first depth, and a second doped region in the active region between the second and third gate structures and having a second horizontal width and a second depth. The second horizontal width is larger than the first horizontal width and the second depth is shallower than the first depth. A distance between the first and second gate structures adjacent to each other is smaller than that between the second and third gate structures adjacent to each other. Related fabrication methods are also described.

Abstract: Disclosed is an air conditioner, in which, when a temperature sensor is rotated, the rotating speed of the temperature sensor is increased or the temperature sensing cycle is elongated in a rotating section where an object does not exist rather than in a rotating section where the object exists. Further, the rotating speed of the temperature sensor is increased or the temperature sensing cycle is elongated if the object is located at a short distance from the air conditioner rather than if the object is located at a normal distance from the air conditioner, and the rotating speed of the temperature sensor is decreased or the temperature sensing cycle is shortened if the object is located at a long distance from the air conditioner rather than if the object is located at a normal distance from the air conditioner.

Abstract: A non-volatile memory cell array, comprising sector selection transistors controlled by a voltage applied to sector selection lines, first through fourth memory cells connected in series to the sector selection transistors, a first common source line connected between the first memory cell and the second memory cell, and a second common source line connected between the third memory cell and the fourth memory cell and separated from the first common source line. A first voltage is applied to the first common source line, and a second voltage different from the first voltage is applied to the second common source line.

Abstract: An air conditioner includes at least one indoor unit and a wired controller connected to the indoor unit through two lines to receive power from the indoor unit and to perform data communication with the indoor unit. Each of the indoor unit and the wired controller includes a communication unit that modulates a low-frequency communication signal into a high-frequency communication signal and transmits the high-frequency signal and demodulates a received high-frequency signal into a low-frequency signal. When a plurality of indoor units and a wired controller perform communication, a communication signal is transmitted after being modulated into a high-frequency signal and linking the high-frequency signal with DC power. This reduces the inductance of an inductor required to separate the linked high-frequency signal into DC power and a communication signal and the capacitance of a capacitor required to link the signal with DC power, reducing PCB size and inductor and capacitor costs.

Abstract: An indoor unit performs a control operation to not supply power to a load device through a power/communication line simultaneously with other indoor units. An air conditioning system may includes an indoor unit including a microcomputer to output a power application signal to supply power to a load device through a power/communication line, and a duplicate power application prevention unit to interrupt the power application signal from the microcomputer when the power is simultaneously applied to the power/communication line by a different indoor unit, to prevent the power from being duplicately applied to the power/communication line.

Abstract: Disclosed herein are a refrigerator and a defrost control method thereof that are capable of sensing an amount of frost formed on an evaporator based on a change amount of absolute humidity in the refrigerator to control a defrost operation. A defrost control method of a refrigerator including a storage chamber and an evaporator to cool the storage chamber, includes sensing absolute humidity in the storage chamber, determining an estimated amount of frost formed on the evaporator using time segments in which the absolute humidity in the storage chamber decreases, and controlling a defrost operation based on the estimated amount of frost. According to the present embodiments, it is possible to perform the defrost operation at the point of time for optimum defrost, thereby maximizing energy efficiency and cooling efficiency.

Abstract: In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.

Abstract: A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode.

Abstract: An air conditioner in which a Carrier Sensing Multiple Access/Collision Avoidance (CSMA/CA) algorithm is provided on a bidirectional RS-485 communication line, and a communication method thereof. The air conditioner includes an RS-485 communication module to transmit and receive data in an RS-485 communication mode, and a microcomputer to determine presence or absence of data on a communication line when data to be transmitted is generated, occupy the communication line if no data is present on the communication line, and then transmit the generated data to the communication line.

Abstract: A damper including a cylinder, a piston inserted in the cylinder, a movable member disposed in the piston to be movable in the cylinder in a length direction of the cylinder, and a weight sensor mounted on an inner surface of the cylinder, facing an end of the piston, to perceive weight loaded on the piston through contact with the movable member. When applied to a washing machine, the damper is capable of perceiving accurate weight of the laundry supplied in the washing machine.

Abstract: An oscillatory wave generating unit and an oscillatory wave sensing unit are installed at both ends of a refrigerant pipe of an evaporator of the cooling system, an amount of frost formed on the refrigerant pipe is determined by comparing a wave form of an oscillatory wave generated from one end of the refrigerant through the oscillatory wave generating unit and a wave form of the oscillatory wave sensed by the other one end of the refrigerant through the oscillatory wave sensing unit, and whether or not a defrosting operation is performed is determined by a result of the determination. The cooling system increases the accuracy in sensing the amount of the frost formed on the evaporator of a refrigerator, a Kimchi refrigerator, or an air conditioner, and respectively starts and ends the defrosting operation at proper points of time, thus enhancing a heat-exchanging performance and increasing energy efficiency.

Abstract: A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode.

Abstract: The present invention is directed to a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a first transistor connected to an nth bitline and a second transistor connected to an (n+1)th bitline. The first transistor and the second transistor are serially coupled between the nth bitline and the (n+1)th bitline. The non-volatile memory device may include a 2-transistor 1-bit unit cell where a drain region and a source region of a memory cell have the same or similar structure. Since a cell array of a non-volatile memory device according to the invention may include a 2-transistor 2-bit unit cell, storage capacity of the non-volatile memory device may be doubled.

Abstract: A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.

Abstract: A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.