Patents by Inventor Dohyun Lee
Dohyun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11090653Abstract: Microfluidic systems and methods to generate and analyze microcapsules comprising biological sample, such as for example, single cells, cellular contents, microspore, protoplast, are disclosed. The microcapsules comprising the biological sample can be preserved by a polymerization process that forms a hydrogel around the biological sample. The hydrogel microcapsules can be trapped in a trapping array or collected in an output reservoir and subject to one or more assays. The trapping array or the output reservoir can be disposed over a porous layer that can filter the continuous phase (e.g., oil) in which the microcapsules are dispersed in the microfluidic device. The pores of the porous layer are configured to be smaller than the size of the microcapsules to prevent the flow of the microcapsules through the porous layer.Type: GrantFiled: October 10, 2017Date of Patent: August 17, 2021Assignees: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, PIONEER HI-BRED INTERNATIONAL, INC.Inventors: Abraham P. Lee, Dohyun Lee, Yue Yun
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Publication number: 20210167004Abstract: A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.Type: ApplicationFiled: June 5, 2020Publication date: June 3, 2021Inventors: Donghee SEO, Heonbok LEE, Tae-Yeol KIM, Daeyong KIM, Dohyun LEE
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Publication number: 20210100728Abstract: The present invention relates to a pharmaceutical composition comprising piperonylic acid as an effective ingredient for anti-aging or regenerating the skin. A composition according to the present invention utilizes piperonylic acid that various plant species naturally contain therein and thus does not cause side effects. Piperonylic acid activates signals associated with cell survival, growth, and proliferation to exhibit the effect of increasing the resistance and survival of skin cells against external stimuli and enhancing the regeneration of the skin damaged due to external stimuli or senescence. In addition, piperonylic acid of the present invention has a similar function to EGF, but is stable and small in size in contrast to EGF. Thus, piperonylic acid of the present invention has the advantage of being able to easily move to the skin basal layer across the skin barrier and perform its function.Type: ApplicationFiled: July 23, 2018Publication date: April 8, 2021Inventors: Kyong Tai KIM, Dohyun LEE, Jinsun LIM
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Publication number: 20200238288Abstract: Methods and devices for single cell analysis using fluorescence lifetime imaging microscopy (FLIM) are disclosed. The methods utilize microfluidic devices which use traps to immobilize cells for FLIM analysis. The analysed cells may be sorted before or after imaging and may be plant, animal, or bacterial cells. Analysis of the FLIM data may use a phasor plot and may be used to identify a metabolic pattern of the single cells.Type: ApplicationFiled: April 13, 2020Publication date: July 30, 2020Inventors: Abraham P. Lee, Michelle A. Digman, Dohyun Lee, Xuan Li, Ning Ma, Yue Yun
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Patent number: 10707126Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.Type: GrantFiled: January 24, 2020Date of Patent: July 7, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Dohyun Lee, Youngwoo Park, Junghoon Park, Jaeduk Lee
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Publication number: 20200161179Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.Type: ApplicationFiled: January 24, 2020Publication date: May 21, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Dohyun LEE, Youngwoo PARK, Junghoon PARK, Jaeduk LEE
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Publication number: 20200055052Abstract: Microfluidic systems and methods to generate and analyze microcapsules comprising biological sample, such as for example, single cells, cellular contents, microspore, protoplast, are disclosed. The microcapsules comprising the biological sample can be preserved by a polymerization process that forms a hydrogel around the biological sample. The hydrogel microcapsules can be trapped in a trapping array or collected in an output reservoir and subject to one or more assays. The trapping array or the output reservoir can be disposed over a porous layer that can filter the continuous phase (e.g., oil) in which the microcapsules are dispersed in the microfluidic device. The pores of the porous layer are configured to be smaller than the size of the microcapsules to prevent the flow of the microcapsules through the porous layer.Type: ApplicationFiled: October 10, 2017Publication date: February 20, 2020Inventors: Abraham P. Lee, Dohyun Lee, Yue Yun
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Patent number: 10566233Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.Type: GrantFiled: August 7, 2019Date of Patent: February 18, 2020Assignee: Samsung Electronics Co., LtdInventors: Dohyun Lee, Youngwoo Park, Junghoon Park, Jaeduk Lee
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Publication number: 20190363012Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.Type: ApplicationFiled: August 7, 2019Publication date: November 28, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Dohyun Lee, Youngwoo Park, Junghoon Park, Jaeduk Lee
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Patent number: 10418278Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.Type: GrantFiled: December 29, 2017Date of Patent: September 17, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Dohyun Lee, Youngwoo Park, Junghoon Park, Jaeduk Lee
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Patent number: 10229927Abstract: A semiconductor device includes a lower stack structure including lower gate electrodes and lower insulating layers that are alternately and repeatedly stacked on a substrate. The semiconductor device includes an upper stack structure including upper gate electrodes and upper insulating layers that are alternately and repeatedly stacked on the lower stack structure. A lower channel structure penetrates the lower stack structure. An upper channel structure penetrates and is connected to the upper stack structure. A lower vertical insulator is disposed between the lower stack structure and the lower channel structure. The lower channel structure includes a first vertical semiconductor pattern connected to the substrate, and a first connecting semiconductor pattern disposed on the first vertical semiconductor pattern.Type: GrantFiled: May 29, 2015Date of Patent: March 12, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dohyun Lee, Jaegoo Lee, Young-Jin Kwon, Youngwoo Park, Jaeduk Lee
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Patent number: 10032789Abstract: Provided is a three-dimensional semiconductor memory device including a peripheral logic structure on a semiconductor substrate to include peripheral logic circuits and a lower insulating gapfill layer, a horizontal semiconductor layer on the peripheral logic structure, stacks on the horizontal semiconductor layer, each of the stacks including a plurality of electrodes vertically stacked on the horizontal semiconductor layer, and a plurality of vertical structures passing through the stacks and connected to the horizontal semiconductor layer. The horizontal semiconductor layer may include a first semiconductor layer disposed on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities of a first impurity concentration, and a second semiconductor layer disposed on the first semiconductor layer and doped with first conductivity type impurities of a second impurity concentration lower than the first impurity concentration or undoped.Type: GrantFiled: July 13, 2016Date of Patent: July 24, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dohyun Lee, Younghwan Son, Minyeong Song, Youngwoo Park, Jaeduk Lee
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Publication number: 20180122695Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.Type: ApplicationFiled: December 29, 2017Publication date: May 3, 2018Inventors: Dohyun LEE, Youngwoo PARK, Junghoon PARK, Jaeduk LEE
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Patent number: 9875931Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.Type: GrantFiled: July 5, 2016Date of Patent: January 23, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Dohyun Lee, Youngwoo Park, Junghoon Park, Jaeduk Lee
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Publication number: 20170186758Abstract: Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns.Type: ApplicationFiled: March 14, 2017Publication date: June 29, 2017Inventors: Changhyun LEE, Dohyun LEE, Youngwoo PARK, Su Jin AHN, Jaeduk LEE
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Patent number: 9595346Abstract: Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns.Type: GrantFiled: May 18, 2016Date of Patent: March 14, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Changhyun Lee, Dohyun Lee, Youngwoo Park, Su Jin Ahn, Jaeduk Lee
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Publication number: 20170047343Abstract: Provided is a three-dimensional semiconductor memory device including a peripheral logic structure on a semiconductor substrate to include peripheral logic circuits and a lower insulating gapfill layer, a horizontal semiconductor layer on the peripheral logic structure, stacks on the horizontal semiconductor layer, each of the stacks including a plurality of electrodes vertically stacked on the horizontal semiconductor layer, and a plurality of vertical structures passing through the stacks and connected to the horizontal semiconductor layer. The horizontal semiconductor layer may include a first semiconductor layer disposed on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities of a first impurity concentration, and a second semiconductor layer disposed on the first semiconductor layer and doped with first conductivity type impurities of a second impurity concentration lower than the first impurity concentration or undoped.Type: ApplicationFiled: July 13, 2016Publication date: February 16, 2017Inventors: Dohyun LEE, Younghwan SON, Minyeong SONG, YOUNGWOO PARK, Jaeduk LEE
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Publication number: 20170011996Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.Type: ApplicationFiled: July 5, 2016Publication date: January 12, 2017Inventors: Dohyun LEE, Youngwoo Park, Junghoon Park, Jaeduk Lee
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Publication number: 20160343450Abstract: Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns.Type: ApplicationFiled: May 18, 2016Publication date: November 24, 2016Inventors: Changhyun LEE, Dohyun LEE, Youngwoo PARK, Su Jin AHN, Jaeduk LEE
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Patent number: 9299707Abstract: Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.Type: GrantFiled: January 8, 2014Date of Patent: March 29, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jaeduk Lee, Youngwoo Park, Jintaek Park, Dohyun Lee, Kohji Kanamori