Patents by Inventor Dohyun Lee

Dohyun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160005760
    Abstract: A semiconductor device includes a lower stack structure including lower gate electrodes and lower insulating layers that are alternately and repeatedly stacked on a substrate. The semiconductor device includes an upper stack structure including upper gate electrodes and upper insulating layers that are alternately and repeatedly stacked on the lower stack structure. A lower channel structure penetrates the lower stack structure. An upper channel structure penetrates and is connected to the upper stack structure. A lower vertical insulator is disposed between the lower stack structure and the lower channel structure. The lower channel structure includes a first vertical semiconductor pattern connected to the substrate, and a first connecting semiconductor pattern disposed on the first vertical semiconductor pattern.
    Type: Application
    Filed: May 29, 2015
    Publication date: January 7, 2016
    Inventors: Dohyun Lee, Jaegoo Lee, Young-Jin Kwon, Youngwoo Park, Jaeduk Lee
  • Patent number: 8791520
    Abstract: Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaeduk Lee, Albert Fayrushin, ByungKyu Cho, Jungdal Choi, Sunghoi Hur, Kwang Soo Seol, Dohyun Lee
  • Publication number: 20140197469
    Abstract: Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.
    Type: Application
    Filed: January 8, 2014
    Publication date: July 17, 2014
    Inventors: Jaeduk Lee, Youngwoo Park, Jintaek Park, Dohyun Lee, Kohji Kanamori
  • Patent number: 8129049
    Abstract: Disclosed herein is a jelly-roll type electrode assembly (“jelly-roll”) of a cathode/separator/anode structure, wherein the jelly-roll is constructed in a structure in which each electrode has active material layers formed on opposite major surfaces of a sheet-type current collector, the loading amount of an active material for the inner active material layer, constituting the inner surface of each sheet when each sheet is wound, is less than that of an active material for the outer active material layer, constituting the outer surface of each sheet when each sheet is wound, and the loading amount of the active material for the inner active material layer gradually increases from the central region of each wound sheet to the outermost region of each wound sheet.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: March 6, 2012
    Assignee: LG Chem, Ltd.
    Inventors: Jong Hee Kim, Dongmyung Kim, Hyungook Yoon, Yong Jeong Kim, Joo-Hwan Sung, Seung W. Chu, Sung-Pil Yoon, Dohyun Lee
  • Publication number: 20110169068
    Abstract: Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.
    Type: Application
    Filed: January 7, 2011
    Publication date: July 14, 2011
    Inventors: JAEDUK LEE, Albert Fayrushin, ByungKyu Cho, Jungdal Choi, Sunghoi Hur, Kwang Soo Seol, Dohyun Lee
  • Publication number: 20100104930
    Abstract: Disclosed herein is a jelly-roll type electrode assembly (“jelly-roll”) of a cathode/separator/anode structure, wherein the jelly-roll is constructed in a structure in which each electrode has active material layers formed on opposite major surfaces of a sheet-type current collector, the loading amount of an active material for the inner active material layer, constituting the inner surface of each sheet when each sheet is wound, is less than that of an active material for the outer active material layer, constituting the outer surface of each sheet when each sheet is wound, and the loading amount of the active material for the inner active material layer gradually increases from the central region of each wound sheet to the outermost region of each wound sheet.
    Type: Application
    Filed: March 24, 2008
    Publication date: April 29, 2010
    Applicant: LG Chem, Ltd.
    Inventors: Jong Hee Kim, Dongmyung Kim, Hyungook Yoon, Yong Jeong Kim, Joo-Hwan Sung, Seung W. Chu, Sung-Pil Yoon, Dohyun Lee
  • Publication number: 20080050655
    Abstract: Provided is a cathode mix for a lithium secondary battery, comprising a cathode active material, a conductive material and a binder, wherein the cathode mix uses a mixture of a flake-like carbon material (a), and a spherical chain-like carbon material (b) in a weight ratio (a/b) of 0.01 to 1 as the conductive material; and a lithium secondary battery comprising the same. Use of the conductive material according to the present invention can achieve simultaneous improvements in conductivity and loading density of the cathode mix, provide excellent discharge characteristics even with increased loading amounts of the cathode mix, and secure performance uniformity between the battery cells.
    Type: Application
    Filed: July 12, 2007
    Publication date: February 28, 2008
    Applicant: LG CHEM, LTD.
    Inventors: Seung Woo CHU, Sung-Pil YOON, Dohyun LEE, Dongmyung KIM, Joo-Hwan SUNG, Yong Jeong KIM, Hyungook YOON, Jong Hee KIM