Patents by Inventor Dominic Maier

Dominic Maier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180086632
    Abstract: A method for fabricating an electronic device is disclosed. In one example, the method comprises providing a semiconductor wafer, forming a plurality of cavities into the semiconductor wafer, filling a stabilization material into the cavities, fabricating a temporary panel by applying a cap sheet onto the semiconductor wafer, the cap sheet covering the cavities, singulating the temporary panel into a plurality of semiconductor devices, fabricating an embedded wafer by embedding the semiconductor devices in an encapsulant, removing the cap sheet of each one of the semiconductor devices, and singulating the embedded wafer into a plurality of electronic devices.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 29, 2018
    Applicant: Infineon Technologies AG
    Inventors: Dominic Maier, Joachim Mahler, Daniel Porwol, Alfred Sigl
  • Publication number: 20180022601
    Abstract: The method comprises fabricating a semiconductor panel comprising a plurality of semiconductor devices, fabricating a cap panel comprising a plurality of caps, bonding the cap panel onto the semiconductor panel so that each one of the caps covers one or more of the semiconductor devices, and singulating the bonded panels into a plurality of semiconductor modules.
    Type: Application
    Filed: July 17, 2017
    Publication date: January 25, 2018
    Applicant: Infineon Technologies AG
    Inventors: Claus Waechter, Edward Fuergut, Bernd Goller, Michael Ledutke, Dominic Maier
  • Patent number: 9806056
    Abstract: Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: October 31, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Wachter, Dominic Maier, Thomas Kilger
  • Publication number: 20170283247
    Abstract: A semiconductor device includes a microelectromechanical system (MEMS) die, a lid, and an integrated circuit die. The lid is over the MEMS die and defines a cavity between the lid and the MEMS die. The integrated circuit die is attached to an inner side of the lid. The integrated circuit die is electrically coupled to the MEMS die.
    Type: Application
    Filed: April 4, 2016
    Publication date: October 5, 2017
    Applicant: Infineon Technologies AG
    Inventors: Thorsten Meyer, Dominic Maier, Johannes Lodermeyer, Bernd Stadler
  • Publication number: 20170284951
    Abstract: According to an embodiment, a sensor package includes an electrically insulating substrate including a cavity in the electrically insulating substrate, an ambient sensor, an integrated circuit die embedded in the electrically insulating substrate, and a plurality of conductive interconnect structures coupling the ambient sensor to the integrated circuit die. The ambient sensor is supported by the electrically insulating substrate and arranged adjacent the cavity.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Inventors: Stephan Pindl, Daniel Lugauer, Dominic Maier, Alfons Dehe
  • Publication number: 20170276646
    Abstract: Embodiments of the present disclosure provide an apparatus for determining a characteristic of a fluid. The apparatus may include a device configured to determine a hydrodynamic pressure of the fluid. The apparatus may further include a sensor configured to determine a hydrostatic pressure of the fluid or at least one component of the fluid. The apparatus may also include a common substrate on which the sensor and the device configured to determine a hydrodynamic pressure of the fluid may be commonly arranged, and an ASIC (Application Specific Integrated Circuit) which may be electrically coupled with at least one of the device or the sensor. The ASIC may be at least partially embedded in the common substrate.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 28, 2017
    Inventors: Rui Miguel Moreira Araujo, Bernd Goller, Dominic Maier
  • Publication number: 20170236776
    Abstract: A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.
    Type: Application
    Filed: February 17, 2016
    Publication date: August 17, 2017
    Applicant: Infineon Technologies AG
    Inventors: Ngoc-Hoa Huynh, Franz-Xaver Muehlbauer, Claus Waechter, Veronika Huber, Dominic Maier, Thomas Kilger, Saverio Trotta, Ashutosh Baheti, Georg Meyer-Berg, Maciej Wojnowski
  • Patent number: 9725303
    Abstract: A semiconductor device includes a microelectromechanical system (MEMS) die, an encapsulation material, a via element, a non-conductive lid, and a conductive layer. The encapsulation material laterally surrounds the MEMS die. The via element extends through the encapsulation material. The non-conductive lid is over the MEMS die and defines a cavity. The conductive layer is over the MEMS die and the encapsulation material and is electrically coupled to the via element.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: August 8, 2017
    Assignee: Infineon Technologies AG
    Inventors: Dominic Maier, Franz-Xaver Muehlbauer, Thomas Kilger
  • Patent number: 9711462
    Abstract: In various embodiments, a package arrangement may be provided. The package arrangement may include at least one chip. The package arrangement may further include encapsulation material at least partially encapsulating the chip. The package arrangement may also include a redistribution structure over a first side of the chip. The package arrangement may further include a metal structure over a second side of the chip. The second side may be opposite the first side. The package arrangement may additionally include at least one of a semiconductor structure and an electrically conductive plastic material structure electrically coupled to the redistribution structure and the metal structure to form a current path between the redistribution structure and the metal structure.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: July 18, 2017
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Dominic Maier, Ulrich Wachter, Daniel Kehrer
  • Patent number: 9487392
    Abstract: A method of packaging integrated circuits includes providing a molded substrate that has a plurality of first semiconductor dies and a plurality of second semiconductor dies laterally spaced apart from one another and covered by a molding compound. The molding compound is thinned to expose at least some of the second semiconductor dies. The exposed second semiconductor dies are removed to form cavities in the molded substrate. A plurality of third semiconductor dies are inserted in the cavities formed in the molded substrate, and electrical connections are formed to the first semiconductor dies and to the third semiconductor dies.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: November 8, 2016
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Wachter, Dominic Maier, Thomas Kilger
  • Publication number: 20160311679
    Abstract: A method of producing a chip package is described. A plurality of chips is provided on a first wafer. Each chip has a cavity which opens to a first main face of the chip. The cavities are filled or covered temporarily. The chips are then singulated. The singulated chips are embedded in an encapsulation material, and then the cavities are re-exposed.
    Type: Application
    Filed: April 26, 2016
    Publication date: October 27, 2016
    Inventors: Dominic Maier, Alfons Dehe, Thomas Kilger, Markus Menath, Franz Xaver Muehlbauer, Daniel Porwol, Juergen Wagner
  • Publication number: 20160297672
    Abstract: A semiconductor device having a lid, and method of making a semiconductor device having a lid is disclosed. The semiconductor device includes a substrate. A device is positioned at the substrate. A lid made of a semiconductor material is positioned over the device to form a protective cavity about the device. The lid is formed using a semiconductor process. In other examples, the lid may be made of a nonconductive material, such as a polymer material. The lids may be formed as part of a batch process.
    Type: Application
    Filed: April 13, 2015
    Publication date: October 13, 2016
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Franz-Xaver Muehlbauer, Dominic Maier, Thomas Kilger
  • Publication number: 20160218039
    Abstract: A method for handling a product substrate includes bonding a carrier to the product substrate. A layer of a permanent adhesive is applied onto a surface of the carrier. A structured intermediate layer is provided. The applied permanent adhesive bonds the carrier to the product substrate. The structured intermediate layer is arranged between the product substrate and the carrier. A surface of the structured intermediate layer and a surface of the permanent adhesive are in direct contact to a surface of the product substrate. The structured intermediate layer decreases a bonding strength between the product substrate and the carrier.
    Type: Application
    Filed: January 20, 2016
    Publication date: July 28, 2016
    Inventors: Georg Meyer-Berg, Claus von Waechter, Michael Bauer, Holger Doepke, Dominic Maier, Daniel Porwol, Tobias Schmidt
  • Patent number: 9368435
    Abstract: In an embodiment, an electronic component includes a dielectric layer, a semiconductor device embedded in the dielectric layer, an electrically conductive substrate, a redistribution layer having a first surface and a second surface providing at least one outer contact, and a first electrically conductive member. The semiconductor device has a first surface including at least one first contact pad and a second surface including at least one second contact pad. The second contact pad is mounted on the electrically conductive substrate. The first electrically conductive member includes at least one stud bump and extends between the electrically conductive substrate and the first surface of the redistribution layer.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: June 14, 2016
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Klaus Schiess, Dominic Maier, Chooi Mei Chong
  • Publication number: 20160163674
    Abstract: Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.
    Type: Application
    Filed: February 15, 2016
    Publication date: June 9, 2016
    Inventors: Ulrich Wachter, Dominic Maier, Thomas Kilger
  • Publication number: 20160086876
    Abstract: In an embodiment, an electronic component includes a dielectric layer, a semiconductor device embedded in the dielectric layer, an electrically conductive substrate, a redistribution layer having a first surface and a second surface providing at least one outer contact, and a first electrically conductive member. The semiconductor device has a first surface including at least one first contact pad and a second surface including at least one second contact pad. The second contact pad is mounted on the electrically conductive substrate. The first electrically conductive member includes at least one stud bump and extends between the electrically conductive substrate and the first surface of the redistribution layer.
    Type: Application
    Filed: September 23, 2014
    Publication date: March 24, 2016
    Inventors: Ralf Otremba, Klaus Schiess, Dominic Maier, Chooi Mei Chong
  • Patent number: 9275878
    Abstract: Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: March 1, 2016
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Wachter, Dominic Maier, Thomas Kilger
  • Patent number: 9147585
    Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: September 29, 2015
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kilger, Ulrich Wachter, Dominic Maier, Gottfried Beer
  • Patent number: 9099454
    Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: August 4, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Wachter, Veronika Huber, Thomas Kilger, Ralf Otremba, Bernd Stadler, Dominic Maier, Klaus Schiess, Andreas Schlögl, Uwe Wahl
  • Publication number: 20150091171
    Abstract: Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 2, 2015
    Inventors: Ulrich Wachter, Dominic Maier, Thomas Kilger