Abstract: In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site.

Abstract: In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site.

Abstract: In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site.

Abstract: A method for selectively plating a leadframe (1100) by oxidizing selected areas (401, 402, 403, 404) of the leadframe made of a first metal (102) and then depositing a layer (901) of a second metal onto un-oxidized areas.

Abstract: A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.

Abstract: A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.

Abstract: A packaged semiconductor device including a leadframe made of a first metal, the leadframe including structures with surfaces and sidewalls; capacitors attached to surface portions of the leadframe structures, the capacitors having sidewalls coplanar with structure sidewalls; the capacitors including a foil of conductive material attached to the structure surface, the conductive material having pores covered by oxide and filled with conductive polymer, the capacitors topped by electrodes made of a second metal.

Abstract: A method for fabricating a packaged semiconductor device begins by placing a first mask on a foil of porous conductive material bonded on a strip of a first metal. The surface of the conductive material and the inside of the pores are oxidized. The first mask leaves areas unprotected. The pores of the unprotected areas are filled with a conductive polymeric compound. A layer of a second metal is deposited on the conductive polymeric compound in the unprotected areas. The first mask is removed to expose un-oxidized conductive material. The foil thickness of the un-oxidized conductive material is removed to expose the underlying first metal. This creates sidewalls of the foil and leaves un-removed the capacitor areas covered by the second metal. A second mask is placed on the strip, the second mask defines a plurality of leadframes having chip pads and leads, and protecting the capacitor areas. The portions of the first metal exposed by the second mask are removed.

Abstract: In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site.

Abstract: A semiconductor device (100) includes a leadframe having a chip pad (110) and a lead (111) with a first end (112) proximate to the pad and a second end (113) remote from the pad, the leadframe having a base metal (120) including copper and a stack of a plated first layer (121) of nickel in contact with the base metal and a plated second layer (122) of a noble metal in contact with the nickel layer, the second lead end free of the noble metal. Further included is a copper wire (104) having a ball bond (104a) on a semiconductor chip (101) attached to the chip pad, and a stitch bond (104b) on the proximate lead end, the stitch bond penetrating the second layer; furthermore a packaging compound (130) encapsulating the chip, the wire, and the first end of the lead, the compound leaving the second end of the lead un-encapsulated; and the unencapsulated second lead end covered with a plated third layer (123) of solder.

Abstract: A method for fabricating a leadframe strip is disclosed. A leadframe pattern is formed from flat sheet of base metal. Additional metal layers are plated on patterned tape of base metal and the leadframe surface is roughed. A first set of leadframe areas is planished. A second set of leadframe areas are offsetted and the tape is cut into strips.

Abstract: A semiconductor device includes a leadframe, a semiconductor chip, a packaging compound. The leadframe has a pad with straps. Leads on the leadframe include first and second portions. The pad, the straps, and the leads have a mechanically rough surface. The semiconductor chip is attached to the pad and wire bonded to the first lead portions. A packaging compound encapsulates the chip, the pad, the straps, the bonding wires and the first lead portions. The second lead portions are left un-encapsulated. The strap ends are exposed on the surface of the package. At least one of the straps includes a portion adjacent to the exposed end. This portion having a mechanically smooth surface transitioning by a step into the rough surface of the remainder of the strap.

Abstract: A semiconductor device (100) includes a leadframe having a chip pad (110) and a lead (111) with a first end (112) proximate to the pad and a second end (113) remote from the pad, the leadframe having a base metal (120) including copper and a stack of a plated first layer (121) of nickel in contact with the base metal and a plated second layer (122) of a noble metal in contact with the nickel layer, the second lead end free of the noble metal. Further included is a copper wire (104) having a ball bond (104a) on a semiconductor chip (101) attached to the chip pad, and a stitch bond (104b) on the proximate lead end, the stitch bond penetrating the second layer; furthermore a packaging compound (130) encapsulating the chip, the wire, and the first end of the lead, the compound leaving the second end of the lead un-encapsulated; and the unencapsulated second lead end covered with a plated third layer (123) of solder.

Abstract: An integrated circuit package has a leadframe having an open space extending therethrough. An integrated circuit device is attached to a portion of the upper surface of the leadframe. A shunt is located within the open space such that it is not in contact with any portion of the leadframe.

Abstract: A system has a leadframe strip and a plurality of integrated circuit dies are each encapsulated in an encapsulant. The encapsulant has a plurality of first cuts and a plurality of second cuts therein. A fixture holds the package in said plurality of first cuts while said plurality of second cuts are made.

Abstract: A metal leadframe strip (500) for semiconductor devices comprising a plurality of sites (510) for assembling semiconductor chips, the sites alternating with zones (520) for connecting the leadframe to molding compound runners; the sites (510) having mechanically rough and optically matte surfaces (511, 512); the zones (520) having at least portions with mechanically flattened and optically shiny metal surfaces (521, 522); and the flattened surface portions transitioning into the rough surface portions by a step.

Abstract: A metal leadframe strip (500) for semiconductor devices is described. The leadframe strip has a plurality of sites (510) for assembling semiconductor chips. The sites alternate with zones (520) for connecting the leadframe to molding compound runners. The sites (510) have mechanically rough and optically matte surfaces (511, 512). The zones (520) have at least portions with mechanically flattened and optically shiny metal surfaces (521, 522). The flattened surface portions transition into the rough surface portions by a step.

Abstract: A method for fabricating a leadframe strip is disclosed. A leadframe pattern is formed from flat sheet of base metal. Additional metal layers are plated on patterned tape of base metal and the leadframe surface is roughed. A first set of leadframe areas is planished. A second set of leadframe areas are offsetted and the tape is cut into strips.

Abstract: A metal leadframe strip (500) for semiconductor devices is described. The leadframe strip has a plurality of sites (510) for assembling semiconductor chips. The sites alternate with zones (520) for connecting the leadframe to molding compound runners. The sites (510) have mechanically rough and optically matte surfaces (511, 512). The zones (520) have at least portions with mechanically flattened and optically shiny metal surfaces (521, 522). The flattened surface portions transition into the rough surface portions by a step.

Abstract: Strip testing is applied to a plurality of integrated circuit dies that are each encapsulated in an encapsulant, that each have a set of externally accessible leads connected thereto, and that are electrically isolated from one another. Provision is made for the strip testing to be performed without mounting the encapsulated integrated circuit dies on a support tape.