Patents by Inventor Donald C. Abbott

Donald C. Abbott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7411303
    Abstract: An apparatus comprising an insulating substrate having first and second surfaces and a plurality of metal-filled vias extending from the first to the second surface. The first and second surfaces have contact pads, each one comprising a connector stack to at least one of the vias. The stack comprises a seed metal layer in contact with the via metal capable of providing an adhesive and conductive layer for electroplating on its surface, a first electroplated support layer secured to the seed metal layer, a second electroplated support layer, and at least one reflow metal bonding layer on the second support layer. The electrolytic plating process produces support layers substantially pure (at least 99.0%), free of unwanted additives such as phosphorus or boron, and exhibiting closely controlled grain sizes. Reflow metal connectors provide attachment to chip contact pads and external parts.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: August 12, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Donald C. Abbott
  • Patent number: 7368328
    Abstract: A semiconductor device having a leadframe comprised of a base metal (110, e.g., copper), a chip mount pad (103) and a plurality of lead segments (104). Each of the segments has a first end (104a) near the mount pad and a second end (104b) remote from the mount pad. The device further has a semiconductor chip (103) attached to the mount pad and electrical interconnections (107) between the chip and the first segment ends. Encapsulation material (120) covers the chip, the bonding wires and the first segment ends, yet leaves the second segment ends exposed. At least portions of the second segment ends have the base metal covered by a layer of solderable metal (130, e.g., nickel) and by an outermost layer of noble metal (140, e.g., stack of palladium and gold).
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: May 6, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Donald C Abbott, Edgar R Zuniga-Ortiz
  • Patent number: 7368807
    Abstract: A method (300) for fabricating a lead frame (100), comprising forming a plurality of external leads (122) in a lead frame material (108), plating a metal (222) on all surfaces of the lead frame material (108), and subsequently forming a plurality of internal leads (124) in the lead frame material (108). The lead frame material (108) may comprise of a portion of a contiguous metal sheeting (204) rolled upon a first coil (202), wherein the contiguous metal sheeting (204) is fed into an external lead stamping apparatus (206), thus forming the external leads (122), and rolled onto a second coil (215). The portion is fed into a plating apparatus and plated with the metal (222), and rolled onto a third coil (218) prior to forming the plurality of internal leads (124). The third coil (218) can be unrolled into an internal lead stamping apparatus (226), thus forming the internal leads (124) of a lead frame (100).
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: May 6, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Donald C Abbott
  • Patent number: 7309909
    Abstract: A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (402) and a plurality of lead segments (403). Covering the base metal are, consecutively, a nickel layer (301) on the base metal, and a continuous layer of noble metal, which consists of a gold layer (201) on the nickel layer, and an outermost palladium layer (202) on the gold layer. A semiconductor chip (410) is attached to the chip mount pad and conductive connections (412) span from the chip to the lead segments. Polymeric encapsulation compound (420) covers the chip, the connections, and portions of the lead segments. In QFN devices with straight sides (501), the compound forms a surface (421) coplanar with the outermost palladium layer (202) on the un-encapsulated leadframe surfaces.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: December 18, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Donald C. Abbott
  • Patent number: 7268415
    Abstract: A semiconductor device having a leadframe comprised of a base metal (110, e.g., copper), a chip mount pad (103) and a plurality of lead segments (104). Each of the segments has a first end (104a) near the mount pad and a second end (104b) remote from the mount pad. The device further has a semiconductor chip (103) attached to the mount pad and electrical interconnections (107) between the chip and the first segment ends. Encapsulation material (120) covers the chip, the bonding wires and the first segment ends, yet leaves the second segment ends exposed. At least portions of the second segment ends have the base metal covered by a layer of solderable metal (130, e.g., nickel) and by an outermost layer of noble metal (140, e.g., stack of palladium and gold).
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: September 11, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Donald C. Abbott, Edgar R. Zuniga-Ortiz
  • Patent number: 7245006
    Abstract: A leadframe for use in the assembly of integrated circuit chips comprising a base metal structure having an adherent layer of nickel covering said base metal; an adherent film of palladium on said nickel layer; and an adherent layer of palladium on said palladium film, selectively covering areas of said leadframe suitable for bonding wire attachment and solder attachment.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: July 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Donald C. Abbott, Michael E. Mitchell, Paul R. Moehle, Douglas W. Romm
  • Patent number: 7217656
    Abstract: A metal structure for a contact pad of a wafer or substrate (101), which have copper interconnecting traces (102) surrounded by a barrier metal layer (103). The wafer or substrate is protected by an insulating overcoat (104). In the structure, the barrier metal layer is selectively exposed by a window (110) in the insulating overcoat. A layer of copper (105), adherent to the barrier metal, conformally covers the exposed barrier metal. Preferably, the copper layer is deposited by sputtering using a shadow mask. A layer of nickel (106) is adherent to the copper layer and a layer of noble metal (106) is adherent to the nickel layer. The noble metal may be palladium, or gold, or a palladium layer with an outermost gold layer. Preferably, the nickel and noble metal layers are deposited by electroless plating.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: May 15, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Howard R. Test, Donald C. Abbott
  • Patent number: 7192809
    Abstract: A method (300) for fabricating a lead frame (100), comprising forming a plurality of external leads (122) in a lead frame material (108), plating a metal (222) on all surfaces of the lead frame material (108), and subsequently forming a plurality of internal leads (124) in the lead frame material (108). The lead frame material (108) may comprise of a portion of a contiguous metal sheeting (204) rolled upon a first coil (202), wherein the contiguous metal sheeting (204) is fed into an external lead stamping apparatus (206), thus forming the external leads (122), and rolled onto a second coil (215). The portion is fed into a plating apparatus and plated with the metal (222), and rolled onto a third coil (218) prior to forming the plurality of internal leads (124). The third coil (218) can be unrolled into an internal lead stamping apparatus (226), thus forming the internal leads (124) of a lead frame (100).
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: March 20, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Donald C. Abbott
  • Patent number: 7179738
    Abstract: An apparatus comprising an insulating substrate (101) having first and second surfaces (101a, 101b) and a plurality of metal-filled vias (102) extending from the first to the second surface. The first and second surfaces have contact pads (103, 104), each one comprising a connector stack to at least one of the vias. The stack comprises a seed metal layer (110, copper) in contact with the via metal capable of providing an adhesive and conductive layer for electroplating on its surface, a first electroplated support layer (111a, copper) secured to the seed metal layer, a second electroplated support layer (111b, nickel), and at least one reflow metal bonding layer (112, palladium, gold) on the second support layer. The electrolytic plating process produces support layers substantially pure (at least 99.0%), free of unwanted additives such as phosphorus or boron, and exhibiting closely controlled grain sizes. Reflow metal connectors (220, 230) provide attachment to chip contact pads and external parts.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: February 20, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Donald C. Abbott
  • Patent number: 7148085
    Abstract: A leadframe for use with integrated circuit chips comprising a plated layer of gold selectively covering areas of said leadframe intended for solder attachment; and said gold layer providing a visual distinction to said areas.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: December 12, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Donald C. Abbott, Paul R. Moehle
  • Patent number: 7064008
    Abstract: A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering the base metal; a plated layer of pure tin on the nickel layer, selectively covering areas of the leadframe intended for attachment to other parts; and a plated layer of palladium on said nickel layer, selectively covering areas of said Leadframe intended for bonding wire attachment.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: June 20, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Donald C. Abbott, Douglas W. Romm
  • Patent number: 6995042
    Abstract: A method for fabricating a leadframe structure comprising a chip mount pad and a plurality of lead segments, each having a first end near the mount pad and a second end remote from said mount pad. The structure is formed from a sheet-like starting material. In a first plating system, the leadframe is plated with a layer of nickel. Next, the second segment ends are selectively masked and a layer of palladium is selectively plated on the nickel layer on the exposed chip pad and first segments ends in a thickness suitable for wire bonding attachment. In a second plating system, the chip pad and first segment ends are selectively masked and a pure tin layer is selectively plated on the nickel layer on the exposed second segment ends in a thickness suitable for parts attachment.
    Type: Grant
    Filed: January 7, 2004
    Date of Patent: February 7, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Donald C. Abbott
  • Patent number: 6953986
    Abstract: A leadframe for use in the assembly of integrated circuit chips comprising a base metal structure having an adherent layer of nickel covering said base metal; an adherent film of palladium on said nickel layer; and an adherent layer of palladium on said palladium film, selectively covering areas of said leadframe suitable for bonding wire attachment and solder attachment.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: October 11, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Donald C. Abbott, Michael E. Mitchell, Paul R. Moehle, Douglas W. Romm
  • Patent number: 6915566
    Abstract: A method for the fabrication of a double-sided electrical interconnection flexible circuit (200) particularly useful as a substrate for an area array integrated circuit package. A copper matrix with studs (203) is pressed through a dielectric film (201) having a copper layer on the opposite surface, thereby forming an intermediate structure for a flex circuit with self-aligned solid copper vias in a one step process. The contacts are reinforced by plating both surfaces with a layer of copper, and conventional processes are used to complete the circuit patterning.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: July 12, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Donald C. Abbott, John E. Cotugno, Robert M. Fritzsche, Robert A. Sabo, Christopher M. Sullivan, David W. West
  • Patent number: 6849806
    Abstract: An electrical apparatus having resistance to atmospheric effects includes at least one electrical device and a packaging structure. The packaging structure substantially encloses the at least one electrical device. The packaging structure includes a corrosion-resisting agent.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: February 1, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Donald C. Abbott, Douglas W. Romm
  • Patent number: 6838757
    Abstract: For a leadframe for use with integrated circuit chips, a continuous strip of sheet-like base metal is pre-plated with a layer of nickel fully covering the base metal, further on one surface with a palladium layer in a thickness suitable for bonding wire attachment, and on the opposite surface with a layer of either palladium or lead-free solder in a thickness suitable for parts attachment. The leadframe structure is then stamped from the sheet so that the base metal is exposed at the stamped edges, enhancing adhesion to molding compounds.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: January 4, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Donald C. Abbott, Michael E. Mitchell, Paul R. Moehle
  • Patent number: 6828660
    Abstract: A leadframe for use in the assembly of integrated circuit (IC) chips, which has first and second surfaces and a base metal structure (606) with an adherent layer (607) of nickel having a rough, non-reflecting surface covering the base metal. This rough nickel enhances adhesion to molding compounds. An adherent layer (608) of smooth, reflective nickel selectively covers the first surface of the leadframe in areas intended for attachment of bonding wires and the IC chip. This smooth nickel facilitates the use of vision systems. A first adherent metal layer (609) is deposited in selected areas of the first leadframe surface for wire bond attachment, and a second adherent metal layer (610) is deposited to provide attachment to external parts.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: December 7, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Donald C. Abbott
  • Publication number: 20040183165
    Abstract: A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of pure tin on said nickel layer, selectively covering areas of said leadframe intended for attachment to other parts; and a plated layer of palladium on said nickel layer, selectively covering areas of said leadframe intended for bonding wire attachment.
    Type: Application
    Filed: January 20, 2004
    Publication date: September 23, 2004
    Inventors: Donald C. Abbott, Douglas W. Romm
  • Publication number: 20040183166
    Abstract: A leadframe for use in the assembly of integrated circuit (IC) chips, which has a base metal structure (506) with an adherent layer (507) of a bondable and solderable electronegative metal. Adhering to the first layer (507) is a layer of a second metal (508), which provides improved adhesion to molding compounds and is deposited thin enough to permit a bond to the first metal. This second metal may be less electronegative than the first metal. A third adherent layer (510), formed of the second metal, is selectively covering leadframe areas intended for attachment to external parts and has a thickness suitable for such attachment.
    Type: Application
    Filed: March 17, 2003
    Publication date: September 23, 2004
    Inventor: Donald C. Abbott
  • Publication number: 20040155321
    Abstract: A method for fabricating a leadframe structure comprising a chip mount pad and a plurality of lead segments, each having a first end near the mount pad and a second end remote from said mount pad. The structure is formed from a sheet-like starting material. In a first plating system, the leadframe is plated with a layer of nickel. Next, the second segment ends are selectively masked and a layer of palladium is selectively plated on the nickel layer on the exposed chip pad and first segments ends in a thickness suitable for wire bonding attachment. In a second plating system, the chip pad and first segment ends are selectively masked and a pure tin layer is selectively plated on the nickel layer on the exposed second segment ends in a thickness suitable for parts attachment.
    Type: Application
    Filed: January 7, 2004
    Publication date: August 12, 2004
    Inventor: Donald C. Abbott