Abstract: A double sided electrical connection flexible circuit particularly useful as a substrate for an area array integrated package, and the method of fabricating the structure is described. A circuit having interconnections on one surface and solder ball contact pads on the second surface are interconnected by copper plated from a single surface in order to avoid entrapment of air pockets. In one embodiment, the conductive vias are formed from a copper film which extends from the solder ball contact pads, which may be indented, providing a well for solder balls in the contact pad.

Abstract: For a leadframe for use with integrated circuit chips, a continuous strip of sheet-like base metal is pre-plated with a layer of nickel fully covering the base metal, further on one surface with a palladium layer in a thickness suitable for bonding wire attachment, and on the opposite surface with a layer of either palladium or lead-free solder in a thickness suitable for parts attachment. The leadframe structure is then stamped from the sheet so that the base metal is exposed at the stamped edges, enhancing adhesion to molding compounds.

Abstract: A bump connection structure and a method of attachment to integrated circuits or packages is provided which comprises a prefabricated core structure coated with solderable metal layers to form a composite bump. Said composite bump is aligned to contact pads of the chip or package which have been coated with solder paste, and the assembly heated to form a metallurgical bond. The prefabricated core structures are comprised of metal, plastic or ceramic of the size and dictated by package standards. The connection structure is preferably lead free.

Abstract: A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of lead-free solder on said nickel layer, selectively covering areas of said leadframe intended for attachment to other parts; and a plated layer of palladium on said nickel layer, selectively covering areas of said leadframe intended for bonding wire attachment.

Abstract: A double-sides electrical interconnection flexible circuit particularly useful as a substrate for an area array integrated circuit package is described. A circuit having interconnection patterns on one surface and solder ball contact pads on the second surface are interconnected by solid copper vias formed from an array of raised studs etched from a metal matrix. In reel to reel format, the etched metal matrix is adhered to one surface of the film and forms the base metal for the solder ball contact pads. The matrix with studs are presses through the dielectric film with a copper layer on the opposite surface, thereby forming an intermediate structure for a flex circuit with self-aligned solid copper vias in a one step process. The contacts are reinforced by plating both surfaces with a layer of copper, and conventional processes are used to complete the circuit patterning.

Abstract: A leadframe having the desirable features of palladium plated leadframes, such as compatibility with both wire bonding and solder reflow, as well as good adhesion to molding compounds is provided by plating the interior lead frame portions with one microinch of palladium and the external leads which contact solder with three microinches of palladium. A low cost method for fabricating the leadframe based on a unique combination of proven processes is provided.

Abstract: A lead frame lead and method of fabrication of the leadframe. A leadframe is formed from one of copper or copper-based material having a layer of an alloy of palladium and nickel and a coating of palladium formed over the alloy on the leadframe. The coating of palladium is from about 3 to about 10 microinches and preferably about 3 microinches. The palladium/nickel layer is from about 10 to about 40 microinches and preferably about 10 microinches and is an alloy having from about 40 to about 90 percent by weight nickel and the remainder essentially palladium. A preferred ratio is 75 percent by weight nickel and 25 percent by weight palladium. A semiconductor device is fabricated by providing a copper or copper-based leadframe and forming a layer of the palladium/nickel alloy over the entire leadframe followed by a palladium layer thereover while maintaining the assembly temperature below about 180 degrees C during subsequent device assembly.

Abstract: A method of fabricating an electrically conductive via in a substrate which includes providing an electrically insulating substrate having first and second opposing surfaces and forming a first layer of electrically conductive material on the first of the opposing surfaces and forming a second layer of electrically conductive material on the second of the opposing surface. In accordance with one embodiment, the second layer has a thickness greater than the electrically insulating layer and no greater than the sum of the thicknesses of the electrically insulating layer and the first layer. In accordance with a second embodiment, the second layer has a thickness greater than the electrically insulating layer and no greater than the sum of the thicknesses of the electrically insulating layer and the first layer. A hole is formed in the first layer having sidewalls. A stud is formed in the second layer aligned with the hole in the first layer.

Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

Abstract: A method of fabricating a ball grid array and the array. The method comprises the steps of providing an electrically insulating substrate and forming an essentially gold-free solder ball attach region and wire bond region secured to the substrate. Formation of the solder ball attach and wire bond regions includes forming a layer of electrically conductive material on the substrate, forming a layer of nickel over the layer of electrically conductive material and forming a layer of palladium over the layer of nickel. After chip attach and gold wire bonding or flip chip bonding, solder balls are then applied to the layer of palladium and the solder balls and solder ball attach regions are heated to a temperature sufficiently high and for a sufficient time so that the solder balls extend through and incorporate therein at least a portion of the layer of said palladium and extend to and attach to the layer of nickel.

Abstract: A method for manufacturing a column grid array semiconductor package (10, 210) may include the steps of providing a substrate material (14, 114, 214) having a first side (16, 116) and a second side (18), forming a plurality of holes (36, 136, 236) in the substrate (14, 114, 214), forming contacts (24, 124,) on the first surface (16, 116) of the substrate (14, 114, 214), filling the plurality of holes (36, 136, 236) with a conductive material (32, 132, 232) to an extent that an extension portion (28, 128, 228) is formed on the second side (18) of the substrate (14, 114, 214) to which an electrical contact may be made. The extension portion (28, 128, 228) may be coated with a capping material (40, 140, 240). The holes (36, 136, 236) may be filled with the conductive material (32, 132, 232) by placing a material (146, 246) over the hole (36, 136, 236) on the first side (16, 116) of the substrate (14, 114, 214) and filling the holes (36, 136, 236) with the conductive material (32, 132, 232).

Abstract: A leadframe and method of fabrication of the leadframe. A leadframe is formed from one of copper or copper-based material and a coating of palladium is formed over the leadframe. Optionally, a layer of from about 10 to about 95 percent copper by weight and the remainder palladium is deposited between the leadframe and the coating of palladium. The coating of palladium is from about 3 to about 10 microinches and preferably about 3 microinches. The palladium/copper layer is from about 5 to about 40 microinches and preferably about 10 microinches. A semiconductor device is fabricated by providing a copper or copper-based lead frame and forming a layer of palladium over the leadframe. Optionally, a layer of palladium and copper is formed between the leadframe and the layer of palladium.

Abstract: The invention is to a method for producing a high surface substrate. A mask is positioned (31) over a substrate to define a deposition area. Thereafter at least two dissimilar materials are simultaneously deposited (32) through the mask onto the deposition area. Then one of the deposited materials is selectively removed (33) to provide a high surface area deposited substrate.

Abstract: A lead frame is plated with palladium and then selected portions of the lead frame leads are spot plated with silver to improve solderability.

Abstract: The invention is to a semiconductor package and the method of making the package. A moisture resistant coating such as a ceramic material is applied over a plastic packaged semiconductor device to seal the package from moisture.

Abstract: This invention relates to lead flames upon which chips (A or B) are mounted prior to encapsulation during IC device packaging. A lead frame structure (6) for manufacturing an IC device comprises a lead frame base (1) including a plurality of leads (10) and four first tie bar portions (16) extending toward a die pad aperture (17). A die pad (2) forms a cross-shaped mounting surface (20) for receiving a chip (30), wherein the mounting surface (20) is smaller than the chip (30), such that perimeter surfaces of the chip (30) are substantially exposed when the chip (30) is mounted on the mounting surface (20). Four second tie bar portions (21) extend from the mounting surface (20) and correspond to the four first tie bar portions (16). The die pad (2) is affixed to the lead frame base (1) and positioned in the aperture (17) by affixing each of the first tie bar portions (16) to a corresponding one of the second tie bar portions (21).

Abstract: A lead frame is plated with palladium and then selected portions of the lead frame leads are spot plated with silver to improve solderability.

Abstract: The invention is to an apparatus and method for applying a plastic material to a lead frame for stabilizing the leads and retaining them in a common plane.

Abstract: A method and apparatus for forming lead frames and eliminating irregularities in the edge (22) of openings etched in the sheet metal from which the lead frame is formed. In a first process, a photo resist coated metal sheet (36) is first etched by a photo chemical process to define the lead frame, and then the lead frame metal sheet (36) is etched in an electrochemical process to remove edge irregularities. In a second process, the entire lead frame is formed in an electrochemical process.

Abstract: This invention relates to lead frames upon which chips (A or B) are mounted prior to encapsulation during IC device packaging. A lead frame structure (6) for manufacturing an IC device comprises a lead frame base (1) including a plurality of leads (10) and four first tie bar portions (16) extending toward a die pad aperture (17). A die pad (2) forms a cross-shaped mounting surface (20) for receiving a chip (30), wherein the mounting surface (20) is smaller than the chip (30), such that perimeter surfaces of the chip (30) are substantially exposed when the chip (30) is mounted on the mounting surface (20). Four second tie bar portions (21) extend from the mounting surface (20) and correspond to the four first tie bar portions (16). The die pad (2) is affixed to the lead frame base (1) and positioned in the aperture (17) by affixing each of the first tie bar portions (16) to a corresponding one of the second tie bar portions (21).