Patents by Inventor Donald Gardner

Donald Gardner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200321678
    Abstract: An antenna mount includes a pivot saddle rotatably coupled to a pivot base. The azimuth angle of an antenna changes as the pivot saddle rotates about the pivot base. The pivot base and the pivot saddle further comprise a unitary folded metal part.
    Type: Application
    Filed: August 23, 2017
    Publication date: October 8, 2020
    Inventors: Ian RENILSON, Thomas Cunningham TULLOCH, James Michael JEFFERSON, Donald GARDNER
  • Patent number: 10068718
    Abstract: Embodiments of the present disclosure are directed towards Faradaic energy storage device structures and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a substrate having a plurality of holes disposed in a surface of the substrate, the plurality of holes being configured in an array of multiple rows and an active material for Faradaic energy storage disposed in the plurality of holes to substantially fill the plurality of holes. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Priyanka Pande, Cary L. Pint, Yang Liu, Wei Jin, Charles Holzwarth, Donald Gardner
  • Publication number: 20160372449
    Abstract: Integrated passive components in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die including a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, and a passive device attached to the first die and coupled to the power supply circuit.
    Type: Application
    Filed: December 24, 2014
    Publication date: December 22, 2016
    Applicant: INTEL CORPORATION
    Inventors: STEFAN RUSU, DONALD GARDNER
  • Publication number: 20160300668
    Abstract: Embodiments of the present disclosure are directed towards Faradaic energy storage device structures and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a substrate having a plurality of holes disposed in a surface of the substrate, the plurality of holes being configured in an array of multiple rows and an active material for Faradaic energy storage disposed in the plurality of holes to substantially fill the plurality of holes. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 16, 2016
    Publication date: October 13, 2016
    Inventors: Priyanka Pande, Cary L. Pint, Yang Liu, Wei Jin, Charles Holzwarth, Donald Gardner
  • Patent number: 9396883
    Abstract: Embodiments of the present disclosure are directed towards Faradaic energy storage device structures and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a substrate having a plurality of holes disposed in a surface of the substrate, the plurality of holes being configured in an array of multiple rows and an active material for Faradaic energy storage disposed in the plurality of holes to substantially fill the plurality of holes. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventors: Priyanka Pande, Cary L. Pint, Yang Liu, Wei Jin, Charles Holzwarth, Donald Gardner
  • Publication number: 20160190113
    Abstract: Integrated passive component in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die molding a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Inventors: SUJIT SHARAN, Ravindranath Mahajan, Stefan Rusu, Donald Gardner
  • Patent number: 9330827
    Abstract: A process of making inductors for integrated circuit packages may involve forming an inductor upon a magnetic film on a package substrate. Conductors coupled either to a die or a voltage converter extend perpendicularly through the film to conductive plates, defining current paths through and across the film.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: May 3, 2016
    Assignee: Intel Corporation
    Inventors: Donald Gardner, Gerhard Schrom, Fabrice Paillet, Shamala Chickamenahalli
  • Publication number: 20140321093
    Abstract: Embodiments of the present disclosure are directed towards Faradaic energy storage device structures and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a substrate having a plurality of holes disposed in a surface of the substrate, the plurality of holes being configured in an array of multiple rows and an active material for Faradaic energy storage disposed in the plurality of holes to substantially fill the plurality of holes. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: April 26, 2013
    Publication date: October 30, 2014
    Inventors: Priyanka Pande, Cary L. Pint, Yang Liu, Wei Jin, Charles Holzwarth, Donald Gardner
  • Patent number: 8361594
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of a magnetic material on a substrate, forming an oxide layer on the first layer of the magnetic material, forming at least one conductive structure on the first magnetic layer, forming a dielectric layer on the at least one conductive structure, forming a second layer of the magnetic material on the at least one conductive structure, and forming a magnetic via coupled to the first and second layers of the magnetic material, wherein the magnetic via comprises a shape to increase inductance of the inductive structure.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: January 29, 2013
    Assignee: Intel Corporation
    Inventors: Donald Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Patent number: 8198965
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: June 12, 2012
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Donald Gardner, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Publication number: 20110220855
    Abstract: A dual action self-cleaning and self-decontaminating coating consisting of a superhydrophobic aspect capable of cleaning the surface by having water droplets moving along the surface remove contaminants and a photochemically active aspect capable of disinfecting the surface by producing hydroxyl radicals in the presence of UV radiation and moisture.
    Type: Application
    Filed: March 12, 2010
    Publication date: September 15, 2011
    Inventors: John D. Weir, Ronald G. Pirich, Dennis J. Leyble, Leonard G. Chorosinski, J. Donald Gardner, JR., Steven Chu
  • Publication number: 20110131797
    Abstract: An inductor may be formed from a magnetic film on a package substrate. Conductors coupled either to a die or a voltage converter extend perpendicularly through the film to conductive plates, defining current paths through and across the film.
    Type: Application
    Filed: February 14, 2011
    Publication date: June 9, 2011
    Inventors: Donald Gardner, Gerhard Schrom, Fabrice Paillet, Shamala Chickamenahalli
  • Patent number: 7911313
    Abstract: An inductor may be formed from a magnetic film on a package substrate. Conductors coupled either to a die or a voltage converter extend perpendicularly through the film to conductive plates, defining current paths through and across the film.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: March 22, 2011
    Assignee: Intel Corporation
    Inventors: Donald Gardner, Gerhard Schrom, Fabrice Paillet, Shamala Chickamenahalli
  • Publication number: 20110043318
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Application
    Filed: November 4, 2010
    Publication date: February 24, 2011
    Inventors: GERHARD SCHROM, DONALD GARDNER, PETER HAZUCHA, FABRICE PAILLET, TANAY KARNIK
  • Patent number: 7843304
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: November 30, 2010
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Donald Gardner, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Publication number: 20100001826
    Abstract: An inductor may be formed from a magnetic film on a package substrate. Conductors coupled either to a die or a voltage converter extend perpendicularly through the film to conductive plates, defining current paths through and across the film.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 7, 2010
    Inventors: Donald Gardner, Gerhard Schrom, Fabrice Paillet, Shamala Chickamenahalli
  • Publication number: 20090267722
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Application
    Filed: April 29, 2009
    Publication date: October 29, 2009
    Inventors: GERHARD SCHROM, DONALD GARDNER, PETER HAZUCHA, FABRICE PAILLET, TANAY KARNIK
  • Patent number: 7538653
    Abstract: An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: May 26, 2009
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Donald Gardner, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Publication number: 20090117325
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of a magnetic material on a substrate, forming an oxide layer on the first layer of the magnetic material, forming at least one conductive structure on the first magnetic layer, forming a dielectric layer on the at least one conductive structure, forming a second layer of the magnetic material on the at least one conductive structure, and forming a magnetic via coupled to the first and second layers of the magnetic material, wherein the magnetic via comprises a shape to increase inductance of the inductive structure.
    Type: Application
    Filed: November 7, 2007
    Publication date: May 7, 2009
    Inventors: Donald Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Patent number: D720585
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: January 6, 2015
    Inventors: Samuel Gardner, Donald Gardner, Hugh Gardner