Abstract: A system, method, and computer program product for interactively viewing output log files in an electronic design automation framework. An interactive log file viewer may be configured to identify text objects (such as warnings and error messages) in log files, to render the text objects in a display according to a registered style, and to define responses triggered by user interface interaction with the text objects. Embodiments may read portions of the log files and use plug-ins to identify, render, and respond as configured, according to the text objects found. Callback actions may provide a user more detailed information corresponding to the text object, such as a tool tip or contextual data, and may highlight and select a corresponding design object in a schematic displayed by an integrated electronic design automation application. An arbitration process may select the best callback action for a given log file.

Abstract: A system, method, and computer program product for facilitating model binning in circuit simulators. Embodiments enable specification of models spanning binning dimensions, such as device width and length, in a model group via inheritable model bins. New simulator modeling syntax and semantics eliminate much of the redundancy and parsing overhead from model parameter specifications in foundry process design kits. Indirect and optional inheritance is also enabled, allowing for fine grain and coarse grain grids in the same model group.

Abstract: Recording and playback of trace log data and video log data for programs is described. In one aspect, a method for viewing log data recorded during execution of a program includes causing a display of recorded images depicting prior visual user interaction with the program during a particular time period. The method also includes causing a display of messages tracing and describing prior execution of the program during the particular time period. The display of the messages and the display of the recorded images are synchronized.

Abstract: A system, method, and computer program product for viewing analog simulation check violations in an EDA framework. Embodiments combine input data tables into a single data table for each check type using SQL inner join operations, create a SQL view of the single data table to list individual check violations, and output the view for user inspection of the corresponding check violations. Embodiments normalize the input data tables to include details of circuit nodes, elements, and paths implicated in the check violations. Additional views combine views of different check types into unified summary tables. Embodiments create a second view to aggregate individual check violations that involve the same circuit objects over time, and output the second view. Output views are self-describing, to enable a single graphical user interface to operate across multiple simulator versions. Metadata tables describe data types presented in various view columns, and user interactions allowed therewith.

Abstract: A system and method for managing analog assertion publication and re-use for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to create, verify, formalize, and publish an analog assertion for a circuit design for subsequent re-use with another circuit design. Embodiments enable analog assertion handling while simultaneously depicting a circuit design in a schematic and/or layout editor window. Embodiments capture referenced circuit objects and parameterize the assertion for numerical values and connectivity. A designer may publish the assertion and annotate it with descriptive metadata, possibly with other assertions of related functionality, to a library accessible by users of analog design and verification tools.

Abstract: Electronic Design Automation software displays parameters of a component in a graphical user interface. According to an embodiment, parameters of a component may be filtered through the use of a query. A Component Parameter Manager may search through parameter fields in a CDF file for components that match the query and emphasize the matching parameters in a graphical user interface. The parameter fields in a CDF file may also be augmented by a separate file to add search instructions or additional parameter fields. The augmentation helps facilitate a search by the Component Parameter Manager. The augmentations to a CDF file may be provided in a editable file separate from the CDF file.

Abstract: A system and method for managing SOA assertion violations and related simulator output. Embodiments transform simulator output into descriptive data regarding SOA violations for relational database storage and processing. The database executes queries on the descriptive data according to user input specifying particular descriptive data and SOA assertion violations of interest, and outputs query results for further user action. Individual and accumulative SOA violations are more easily explored by users, through a search language that facilitates selection rule specification via pre-existing or user-defined filters. Filters may inherit rules and combine them with logical and comparative operators, enabling easy construction of complex selection expressions to provide more intuitive design guidance.

Abstract: A system, method, and computer program product for improving circuit reliability via circuit schematic simulation. A circuit simulator may netlist and simulate a schematic with a reference stimulus and determine whether a circuit component is a candidate for stress analysis, and store candidate component circuit conditions. A stress test simulation may determine if candidate components are stressed by exposure to simulated conditions meeting a stress test criterion, and output information regarding stressed circuit components. Embodiments may simulate analog integrated circuitry, determine MOS component gate oxide layer area according to component length and width, and monitor conditions on components deemed most likely to be defective, including larger MOS components. A circuit simulator plug-in may avoid storing simulation output waveforms or performing layout based analysis.

Abstract: Navigating hierarchical levels of a design using graphical preview images. In one aspect, a method for providing a preview image for a design includes causing a display of a main image depicting a first portion of the design, the design organized into multiple hierarchical levels, each level having a different amount of abstraction of graphical information of the design. A preview image smaller than the main image is displayed, portraying a second portion of the design at a different hierarchical level than the first portion. The preview image is receptive to a selection causing the second portion to be displayed as the main image. Some embodiments allow the preview image to include one or more hotspots that cause a display of another preview image at a different hierarchical level, or to show a connected object connected to a probed first object.

Abstract: A system, method, and computer program product for automatically providing circuit designers with verification information for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to enter verification IP while simultaneously viewing the design IP in a schematic and/or layout editor window. Embodiments maintain the verification IP in a cellview similar to the separate cellviews used for schematic and layout data. Verification IP may be selectively translated into data that is directly exportable to and usable by particular analog and mixed-signal simulators. Embodiments direct design IP and verification IP to a simulator that dynamically stitches both together during circuit verification, and tangibly outputs verification results.

Abstract: A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units (“vunits”), and corresponding analog verification files to contain them. Vunits allow circuit design verification requirement specification via text file. No editing of netlist files containing design IP is required to implement static and dynamic circuit checks, PSL assertions, clock statements, or legacy assertions. Vunits reference a top-level circuit or subcircuits (by name or by specific instance), and the simulator automatically binds vunit contents appropriately during circuit hierarchy expansion. Vunits may be re-used for other design cells, and may be easily processed by text-based design tools. Vunits may be provided via vunit_include statements in a control netlist file, command line arguments, or by directly placing a vunit block into a netlist.

Abstract: A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.

Abstract: An apparatus and method for conducting fault sensitivity analysis of the analog portions of a mixed signal circuit design includes simulating the fault free circuit design, inserting a fault into the analog portion of the circuit design, simulating the circuit design with the fault during a fault interval time period, and determining whether the fault is detectable.

Abstract: Certain embodiments enable image-based stimulus for circuit simulations by extracting a waveform from an image and using that waveform to simulate a circuit. Image-processing aspects may include edge-detection processes to identify a boundary of the waveform in the image.

Abstract: A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.

Abstract: An apparatus and method for conducting fault sensitivity analysis of a digitally calibrated circuit design includes simulating calibration of the circuit design, simulating calibration of the circuit design with a fault in the analog portion of the circuit design, simulating the circuit design with the fault for a fault interval time period, and determining whether the fault is detectable.

Abstract: A netlist description that includes embedded code segments for describing a circuit is preprocessed in order to replace the embedded code segments with corresponding preprocessed code segments, where the preprocessed code segments include netlist code that can be parsed and executed. To perform this preprocessing, programming languages that include scripting operations are identified for the embedded code segments in the netlist description. A pipeline preprocessor that includes preprocessors for the identified programming languages is configured to sequentially process the netlist description and replace the embedded code segments with the corresponding preprocessed code segments.

Abstract: Method and system for verifying data in a database. In one aspect, verifying data includes receiving an indication of at least one policy, the at least one policy including at least one rule. A verification process is initiated on target data by implementing the at least one policy, where implementing the at least one policy includes instantiating and applying the at least one rule. The at least one rule causes at least one verification check to be performed on the target data.

Abstract: A system, method, and computer program product for cell-aware fault model generation. Embodiments determine defects of interest for a cell, typically from cell layout and a transistor-level cell netlist. A circuit simulator performs analog fault simulation on the transistor-level netlist to determine detectable defects from the defects of interest, and detection conditions for the detectable defects. The circuit simulator employs fault sensitivity analysis (FSA) for amenable cells for greatly accelerated fault detection. Embodiments generate and output cell-aware fault models for the detectable defects from the detection conditions, for use in automated test pattern generation.

Abstract: In a system, method, and computer program product for analyzing faults in a circuit design, variation of analog fault coverage as a function of bridge resistance values is computed in a single simulation run. A simulator stores intermediate circuit states for each fault resistance value, and performs short interval simulations that may re-use intermediate states as initial solution estimates for simulation of the next fault resistance value. Initial fault resistance values are reduced during simulation passes to aid simulator convergence. The selected evaluation order of test points, faults, and fault resistance values reduces computational and storage costs. Embodiments enable test engineers to rapidly understand if analog defect tests are only sufficient for identifying defects of a certain type and/or value, and to determine fault coverage variability over a full process space.