Abstract: Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic.

Abstract: Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image and one or more shapes in the image, and causing a display of a cursor. Labels are also displayed, each of the labels associated with a different one of the displayed shapes. The plurality of labels are displayed within a predetermined zone relative to a displayed cursor, and wherein no labels are displayed outside of the zone.

Abstract: Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image and one or more shapes in the image, and causing a display of a cursor on the display device. Labels are displayed on the display device, each label associated with a different displayed shape. One or more of the labels are displayed within a zone of focus of eyes of a user of the graphical interface and one or more of the labels are displayed outside the zone of focus, where the labels displayed in the zone of focus are displayed differently than the labels displayed outside the zone of focus.

Abstract: Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image on a display device with or more shapes, and causing a display of multiple labels on the display device. Each of the labels is associated with a different one of the displayed shapes, and the labels are derived from stored connectivity information for the one or more shapes describing the connections of the shapes.

Abstract: A system, method, and computer program product is disclosed that recycle digital assertions for mixed-signal electronic designs. The approach enables the re-use of pure digital assertions which reference signals that turn out to resolve to analog due to the particular circuit configuration chosen during the verification process.

Abstract: A user specifies layout styles for devices in a circuit schematic, where the layout styles capture features of device arrangements and device correlations. The resulting layout can be simulated by using a computer so that one or more performance metrics can be evaluated for the circuit. In some cases, test chips may be used to determine device correlations for arrangements corresponding to different layout styles.

Abstract: Viewing and editing of a displayed image in a magnified view. In one aspect, a method for displaying a magnified image using a computer system includes causing a display on a display device of a first image, and causing a display on the display device of a second image that is a portion of the first image. The second image has a zoomed-in view that is a closer view of the portion than in the first image. At least one edit is caused to the second image in response to at least one input received at the second image.

Abstract: A method to produce a reverse skip list data structure in a computer readable medium, comprising: inputting streamed data to packets created in a temporary memory so as to create a sequence of packets; upon completion of creation of a packet in the stream, transferring the completed packet from the temporary memory to persistent memory; providing each of a plurality of respective packets with a respective pointer that skips over at least one other packet in the packet sequence and that indicates a location in persistent memory of a different respective packet in the packet sequence that was transferred to persistent memory prior to such providing of the respective pointer.

Abstract: A hierarchical, rule-based, general property visualization and editing system, method, and computer program for circuit designs is provided. A general rules dictionary is created or obtained that determines how the rules will be applied to the circuit design hierarchy. A hierarchical graphical user interface serves both as an entry means for the properties of the design components, and as a visualization means to view the resolved effective value of the property for each component or sub-hierarchy. The visualization means also provides a mechanism to view the rule resolution process so a user can view and understand the effects of all the rules that have an effect on the property and can modify the rules settings to obtain the desired effective property value. A property configuration file is output from the visualization tool and input into the simulator armed with the same general rules dictionary.

Abstract: An improved method for debugging of analog and mixed signal behavioral models during simulation using Newton-Raphson iteration replay. The method according to the invention has substantially modified the prior art solution by limiting the interactive debugging steps in a replay of the last iteration of the accepted timepoints. Using this method, the user only interacts with the simulation during the iteration replay, and only for the accepted solution points. If the user is single stepping through this simulation, the simulator enters interactive mode at each statement during the replay. Similarly, if not single stepping, but a breakpoint has been triggered, the simulator enters the interactive mode at the appropriate statement to honor the breakpoint. While the iteration replay is performed, the system of equations does not need to be solved again. Instead, the solution vector is reinstated from the known solution of the last iteration.

Abstract: An improved method for debugging of analog and mixed signal behavioral models during simulation using Newton-Raphson iteration replay. The method according to the invention has substantially modified the prior art solution by limiting the interactive debugging steps in a replay of the last iteration of the accepted timepoints. Using this method, the user only interacts with the simulation during the iteration replay, and only for the accepted solution points. If the user is single stepping through this simulation, the simulator enters interactive mode at each statement during the replay. Similarly, if not single stepping, but a breakpoint has been triggered, the simulator enters the interactive mode at the appropriate statement to honor the breakpoint. While the iteration replay is performed, the system of equations does not need to be solved again. Instead, the solution vector is reinstated from the known solution of the last iteration.

Abstract: A system and method for generating inline subcircuits that enable a circuit designer to model and simulate circuits that when compared to conventional system and methods reduces the hierarchy from the perspective of the circuit designer, more efficiently models parasitic components, more efficiently parameterizes device models, more effectively creates models that are compatible with other simulation tools, can change the interface of a component without requiring the designer to use an extra layer of hierarchy, provides a more efficient interface by hiding details from the designer, enables hidden monitors and other functional designs to be automatically simulated by hiding these functions from the designer in a design level that is below the design level that is of interest to the designer, such as the geometrical parameter design level, can perform general purpose model binning with automatic selection, can export models and model parameters to other hierarchies without requiring an additional hierarchy in