Patents by Inventor Donald J. O'Riordan
Donald J. O'Riordan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8838559Abstract: A method is provided to evaluate user interaction with a computer user interface (UI) comprising: receiving a property definition that identifies at least one relationship among prescribed string patterns that correspond to one or more UI events; receiving a log file in a computer readable storage device that includes a plurality of respective chunks of information; determining whether the respective chunks of information within the log file includes a respective string pattern that matches at least one of the prescribed string patterns; configuring a processor to produce an indication of whether the property is satisfied based upon the string pattern matching determinations.Type: GrantFiled: February 24, 2011Date of Patent: September 16, 2014Assignee: Cadence Design Systems, Inc.Inventor: Donald J. O'Riordan
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Patent number: 8832612Abstract: A method is provided to convert an analog mixed-signal schematic design to a digital netlist: digital blocks within the schematic design are converted to digital netlist modules; analog blocks within the schematic design are converted to analog netlist modules: at least one digital netlist module includes a first identifier for a component that is shared between at least one digital block and at least one analog block within the schematic design; an analog netlist module that corresponds to the at least one analog block within the design includes a second identifier for the shared component that is different from the first identifier; the analog netlist modules are converted to corresponding digital netlist modules; the first identifier is substituted for the second identifier in the course of translating the analog netlist module that corresponds to the at least one analog block.Type: GrantFiled: November 6, 2013Date of Patent: September 9, 2014Assignee: Cadence Design Systems, Inc.Inventors: Donald J. O'Riordan, Prabal Kanti Bhattacharya, Timothy Martin O'Leary
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Patent number: 8813004Abstract: An apparatus and method for visualizing faults in a circuit design includes simulating faults for a circuit design in a layout and a schematic, editing the layout and schematic to include the simulated fault, and linking the layout and schematic with the fault simulation.Type: GrantFiled: November 21, 2012Date of Patent: August 19, 2014Assignee: Cadence Design Systems, Inc.Inventors: Donald J. O'Riordan, Hao Ji, Joseph M. Swenton
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Patent number: 8762906Abstract: Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic.Type: GrantFiled: April 1, 2010Date of Patent: June 24, 2014Assignee: Cadence Design Systems, Inc.Inventors: Arnold Ginetti, Donald J. O'Riordan, Madhur Sharma
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Patent number: 8732636Abstract: Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic.Type: GrantFiled: April 1, 2010Date of Patent: May 20, 2014Assignee: Cadence Design Systems, Inc.Inventors: Arnold Ginetti, Donald J. O'Riordan, Madhur Sharma
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Patent number: 8711177Abstract: Display of measurements in a graphical design on a computer system. In one aspect, shapes are displayed in an image, and a definition of a defined area of the image is received. One or more measurements are determined for one or more of the shapes displayed within the predefined area, the one or more measurements determined automatically without a user designating endpoints for the measurements. The one or more measurements are displayed as being associated with the one or more shapes.Type: GrantFiled: February 24, 2011Date of Patent: April 29, 2014Assignee: Cadence Design Systems, Inc.Inventors: Chayan Majumder, Donald J. O'Riordan, Harindranath Parameswaran
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Patent number: 8689121Abstract: Management of controls in a graphical user interface (GUI) of a computer system. In one aspect, a command is received to create and display a window in the GUI, the window including one or more controls, each control operative to perform a function of an application in response to selection. An associated scope for each control is determined and indicates an extent of shared use of the control within the GUI. It is determined if a different instance of the control already exists within the scope for the control. If so, resources of the different instance are referenced to be shared for use with the control and new resources are not created for the control. If no different instance exists within the scope, new resources for the control are created and stored. The window and the controls in the GUI are displayed.Type: GrantFiled: May 6, 2010Date of Patent: April 1, 2014Assignee: Cadence Design Systems, Inc.Inventor: Donald J. O'Riordan
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Patent number: 8683400Abstract: A apparatus and method for conducting fault sensitivity analysis of the analog portions of a mixed signal circuit design includes simulating the fault free circuit design, inserting a fault into the analog portion of the circuit design, simulating the circuit design with the fault during a fault interval time period, and determining whether the fault is detectable.Type: GrantFiled: November 21, 2012Date of Patent: March 25, 2014Assignee: Cadence Design Systems, Inc.Inventors: Donald J. O'Riordan, Ilya Yusim, Zhipeng Liu
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Patent number: 8645901Abstract: Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image and one or more shapes in the image, and causing a display of a cursor. Labels are also displayed, each of the labels associated with a different one of the displayed shapes. The plurality of labels are displayed within a predetermined zone relative to a displayed cursor, and wherein no labels are displayed outside of the zone.Type: GrantFiled: December 1, 2009Date of Patent: February 4, 2014Assignee: Cadence Design Systems, Inc.Inventors: Chayan Majumder, Donald J. O'Riordan, Shagufta Siddique
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Patent number: 8601412Abstract: A method is provided to convert an analog mixed-signal schematic design to a digital netlist: digital blocks within the schematic design are converted to digital netlist modules; analog blocks within the schematic design are converted to analog netlist modules: at least one digital netlist module includes a first identifier for a component that is shared between at least one digital block and at least one analog block within the schematic design; an analog netlist module that corresponds to the at least one analog block within the design includes a second identifier for the shared component that is different from the first identifier; the analog netlist modules are converted to corresponding digital netlist modules; the first identifier is substituted for the second identifier in the course of translating the analog netlist module that corresponds to the at least one analog block.Type: GrantFiled: November 18, 2011Date of Patent: December 3, 2013Assignee: Cadence Design Systems, Inc.Inventors: Donald J. O'Riordan, Prabal Kanti Bhattacharya, Timothy Martin O'Leary
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Patent number: 8533626Abstract: Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image and one or more shapes in the image, and causing a display of a cursor on the display device. Labels are displayed on the display device, each label associated with a different displayed shape. One or more of the labels are displayed within a zone of focus of eyes of a user of the graphical interface and one or more of the labels are displayed outside the zone of focus, where the labels displayed in the zone of focus are displayed differently than the labels displayed outside the zone of focus.Type: GrantFiled: December 1, 2009Date of Patent: September 10, 2013Assignee: Cadence Design Systems, Inc.Inventors: Chayan Majumder, Donald J. O'Riordan, Shagufta Siddique
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Publication number: 20130227350Abstract: Recording and playback of trace log data and video log data for programs is described. In one aspect, a method for viewing log data recorded during execution of a program includes causing a display of recorded images depicting prior visual user interaction with the program during a particular time period. The method also includes causing a display of messages tracing and describing prior execution of the program during the particular time period. The display of the messages and the display of the recorded images are synchronized.Type: ApplicationFiled: February 23, 2012Publication date: August 29, 2013Applicant: Cadence Design Systems, Inc.Inventors: Donald J. O'RIORDAN, David VARGHESE
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Patent number: 8438531Abstract: Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image on a display device with or more shapes, and causing a display of multiple labels on the display device. Each of the labels is associated with a different one of the displayed shapes, and the labels are derived from stored connectivity information for the one or more shapes describing the connections of the shapes.Type: GrantFiled: December 1, 2009Date of Patent: May 7, 2013Assignee: Cadence Design Systems, Inc.Inventors: Chayan Majumder, Donald J. O'Riordan, Shagufta Siddique
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Patent number: 8296717Abstract: Disclosed are improved methods, systems, and computer program products for implementing inherited connections for electronic designs. Scoped default connection or global nets are used in inherited connections for default expressions, where the default connection/global net that is applied to a particular portion of the design is scoped by being limited in its application only to certain hierarchical portions of the design.Type: GrantFiled: December 20, 2010Date of Patent: October 23, 2012Assignee: Cadence Design Systems, Inc.Inventor: Donald J. O'Riordan
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Patent number: 8234617Abstract: A system, method, and computer program product is disclosed that recycle digital assertions for mixed-signal electronic designs. The approach enables the re-use of pure digital assertions which reference signals that turn out to resolve to analog due to the particular circuit configuration chosen during the verification process.Type: GrantFiled: October 1, 2009Date of Patent: July 31, 2012Assignee: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar, Donald J. O'Riordan
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Patent number: 8214791Abstract: Certain embodiments of the present invention enable a user to display and edit the effects of inherited connections in a circuit that is characterized as a hierarchical arrangement including cell instances and connectors. The hierarchical arrangement may include a tree structure where the cell instances include devices and the connectors include wires and pins. Property names are associated with connectors for identifying corresponding signal sources, and property-setting expression are associated with cell instances for specifying property-name values and making the corresponding identifications. Displays may include a path along the hierarchical arrangement from a given connector to a corresponding signal source including the effects of property names and property-setting expressions along the path. Displays may enable editing by the user to change property names and property-setting expressions along the path and view corresponding results for the inherited connections.Type: GrantFiled: September 17, 2009Date of Patent: July 3, 2012Assignee: Cadence Design Systems, Inc.Inventor: Donald J. O'Riordan
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Patent number: 8200915Abstract: A method to produce a reverse skip list data structure in a computer readable medium, comprising: inputting streamed data to packets created in a temporary memory so as to create a sequence of packets; upon completion of creation of a packet in the stream, transferring the completed packet from the temporary memory to persistent memory; providing each of a plurality of respective packets with a respective pointer that skips over at least one other packet in the packet sequence and that indicates a location in persistent memory of a different respective packet in the packet sequence that was transferred to persistent memory prior to such providing of the respective pointer.Type: GrantFiled: November 4, 2008Date of Patent: June 12, 2012Assignee: Cadence Design Systems, Inc.Inventors: Ramani Pichumani, Jonathan L. Sanders, Donald J. O'Riordan
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Patent number: 8176463Abstract: A user specifies layout styles for devices in a circuit schematic, where the layout styles capture features of device arrangements and device correlations. The resulting layout can be simulated by using a computer so that one or more performance metrics can be evaluated for the circuit. In some cases, test chips may be used to determine device correlations for arrangements corresponding to different layout styles.Type: GrantFiled: September 17, 2009Date of Patent: May 8, 2012Assignee: Cadence Design Systems, Inc.Inventors: Donald J. O'Riordan, Arthur Schaldenbrand, John O'Donovan
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Publication number: 20110276908Abstract: Management of controls in a graphical user interface (GUI) of a computer system. In one aspect, a command is received to create and display a window in the GUI, the window including one or more controls, each control operative to perform a function of an application in response to selection. An associated scope for each control is determined and indicates an extent of shared use of the control within the GUI. It is determined if a different instance of the control already exists within the scope for the control. If so, resources of the different instance are referenced to be shared for use with the control and new resources are not created for the control. If no different instance exists within the scope, new resources for the control are created and stored. The window and the controls in the GUI are displayed.Type: ApplicationFiled: May 6, 2010Publication date: November 10, 2011Applicant: Cadence Design Systems, Inc.Inventor: Donald J. O'Riordan
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Publication number: 20110161900Abstract: Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic.Type: ApplicationFiled: April 1, 2010Publication date: June 30, 2011Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Arnold Ginetti, Donald J. O'Riordan, Madhur Sharma