Abstract: A device structure and method for a non-volatile semiconductor device comprises a trenched floating gate and a control gate and further includes a source region, a drain region, a channel region, and an inter-gate dielectric layer. The trenched floating gate is formed in a trench etched into the semiconductor substrate. The trenched floating gate has a top surface which is substantially planar with a top surface of the substrate. The source and drain region have a depth approximately equal to or greater than the depth of the trench and partially extend laterally underneath the bottom of the trench. The inter-gate dielectric layer is formed on the top surface of the trenched floating gate, and the control gate is formed on the inter-gate dielectric layer. In one embodiment, the device structure also includes sidewall dopings that are implanted regions formed in the semiconductor substrate which extend substantially vertically along the length of the trench.

Abstract: A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further includes a source region a drain region and a channel region. The source and drain region are laterally separated by the trench in which the trenched polysilicon gate is formed and partially extend laterally beneath the bottom surface of the trench. The channel region is formed in the silicon substrate beneath the bottom surface of the trench. In one embodiment the top surface of the trenched polysilicon gate is substantially planar to the substrate surface. In another embodiment the top surface and a portion of the trenched polysilicon gate are disposed above the substrate surface.

Abstract: A method is provided for obtaining an accurate image of a two-dimensional junction profile of a semiconductor device. Embodiments include sectioning a sample to be analyzed through the active transistor, either at a 90° angle to the planar surface or at a desired angle, as by a focused ion beam (FIB) apparatus. The sectioned transistor can be analyzed directly on the exposed silicon, or the exposed silicon of the cross-section can be passivated with a thin film material such as silicon dioxide, or with an undoped semiconductor material such as silicon or germanium. The electrodes (i.e., source, gate, drain and substrate electrodes) of the sample active transistor are then connected so they can be individually electrically biased. The prepared sample is placed in a conventional voltage contrast SEM, and the electrodes are selectively biased to produce a voltage contrast while being imaged by the voltage contrast SEM, thereby resulting in detailed SEM images of the active regions and depletion spreads.

Abstract: A programmable anti-fuse is formed simultaneously with transistors and other devices on a semiconductor substrate. Embodiments include an anti-fuse comprising a doped active region in the substrate, such as an n+ region, a gate oxide layer, and a gate, such as polysilicon, of a minimum size according to design rules. The anti-fuse is programmed by passing a current through it sufficient to cause its gate oxide layer to fail. The inventive anti-fuse is formed by simply altering the patterning of layers that need to be formed for other devices on the substrate. Therefore, it is formed without added manufacturing costs.

Abstract: A silicon on insulator (SOI) device includes an electrically-conducting interface region along a portion of the interface between the insulator and a semiconductor layer atop the insulator. The electrically-conducting interface region provides a “leaky” electrical coupling between the body and source regions of a transistor device such as a “MOSFET”, thereby reducing floating body effects of the device. A method of forming such a semiconductor device includes forming the electrically-conducting interface region by damaging or implanting materials in the insulator and/or the semiconductor in the vicinity of the interface therebetween. The method may include producing a stepped interface region, such as by etching, in order to aid properly locating the transistor device relative to the electrically-conducting interface region.

Abstract: A method is provided for obtaining an accurate image of a two-dimensional junction profile of a semiconductor device. Embodiments include sectioning a sample to be analyzed through the active transistor, either at a 90° angle to the planar surface or at a desired angle, as by a focused ion beam (FIB) apparatus. The sectioned transistor can be analyzed directly on the exposed silicon, or the exposed silicon of the cross-section can be passivated with a thin film material such as silicon dioxide, or with an undoped semiconductor material such as silicon or germanium. The electrodes (i.e., source, gate, drain and substrate electrodes) of the sample active transistor are then connected so they can be individually electrically biased. A direct current (DC) potential is imposed on an active region of the prepared sample, and a small alternating current (AC) potential is imposed on the DC potential.

Abstract: Method for determining the robustness of a device to soft errors generated by alpha-particle and/or cosmic ray strikes.

Abstract: A method and apparatus for controlling the growth of an oxide, such as a gate oxide, in a semiconductor device manufacturing process takes into consideration the ambient atmospheric pressure in order to reduce the variance in gate oxide thicknesses between wafer lots. The pressure in the oxide diffusion tube is maintained at a constant pressure near the ambient atmospheric pressure during the oxide diffusion process. Alternatively, the furnace time is changed from lot to lot as a function of changes in the ambient atmospheric pressure in order to maintain the gate oxide thickness at a constant value between wafer lots.

Abstract: Complementary metal-oxide-semiconductor (CMOS) transistors (18,22) are formed with vertical channel regions (30,52) on an insulator substrate (14). Highly doped polysilicon gates (44,68) are formed in trenches (36,58) to extend laterally around the channel regions (30,52) as insulatively displaced therefrom by gate insulators (41,62) that are grown on the sidewalls of the trenches (36,58). The transistors (18,22), which are formed in respective mesas (20,24) have deeply implanted source regions (28,50) that are ohmically connected to the semiconductor surface via respective source connector regions (34,70).

Abstract: A device structure and method for a non-volatile semiconductor device comprises a trenched floating gate and a control gate and further includes a source region, a drain region, a channel region, and an inter-gate dielectric layer. The trenched floating gate is formed in a trench etched into the semiconductor substrate. The trenched floating gate has a top surface which is substantially planar with a top surface of the substrate. The source and drain have a depth approximately equal to or greater than the depth of the trench and partially extend laterally underneath the bottom of the trench. The inter-gate dielectric layer is formed on the top surface of the trenched floating gate, and the control gate is formed on the inter-gate dielectric layer. In one embodiment, the device structure also includes sidewall dopings that are implanted regions formed in the semiconductor substrate which extend substantially vertically along the length of the trench.

Abstract: A method and apparatus for controlling the growth of an oxide, such as a gate oxide, in a semiconductor device manufacturing process takes into consideration the ambient atmospheric pressure in order to reduce the variance in gate oxide thicknesses between wafer lots. The pressure in the oxide diffusion tube is maintained at a constant pressure near the ambient atmospheric pressure during the oxide diffusion process. Alternatively, the furnace time is changed from lot to lot as a function of changes in the ambient atmospheric pressure in order to maintain the gate oxide thickness at a constant value between wafer lots.

Abstract: A method for manufacturing a field effect transistor (100) includes steps of forming a gate stack (102) on the surface (114) of a semiconductor substrate (108), and defining source/drain regions (104, 106) on either side of the gate stack and a channel region (130) under the gate stack. The channel region has one end (132) proximate a first source/drain region and another end (134) proximate a second source/drain region. The method further includes forming a masking layer (174) on the surface of the semiconductor substrate. The masking layer has a nominal alignment position and a misalignment tolerance. The method still further includes implanting doping ions in the semiconductor substrate to asymmetrically dope the field effect transistor, including selecting a tilt angle and a rotation angle (B, D, F, H) sufficient to ensure shadowing of one end of the channel region from implantation of the doping ions.

Abstract: A fully recessed device structure and method for low power applications comprises a trenched floating gate, a trenched control gate and a single wrap around buried drain region. The trenched floating gate and the trenched control gate are formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography. The fully recessed structure further comprises a buried source region, and a buried drain region that are each formed in the well junction region laterally separated by the trench. The upper boundaries of the buried source region and the buried drain region are of approximately the same depth as the top surface of the trenched floating gate.

Abstract: A silicon on insulator (SOI) device includes an electrically-conducting interface region along a portion of the interface between the insulator and a semiconductor layer atop the insulator. The electrically-conducting interface region provides a “leaky” electrical coupling between the body and source regions of a transistor device such as a “MOSFET”, thereby reducing floating body effects of the device. A method of forming such a semiconductor device includes forming the electrically-conducting interface region by damaging or implanting materials in the insulator and/or the semiconductor in the vicinity of the interface therebetween. The method may include producing a stepped interface region, such as by etching, in order to aid properly locating the transistor device relative to the electrically-conducting interface region.

Abstract: A method for creating a SOI CMOS type device compatible with bulk CMOS using a bulk CMOS physical layout data base. The method uses the P-well and N-well masks used in fabrication of bulk CMOS devices. The N-well and P-well regions are fabricated by implanting the appropriate dopants above and below the buried oxide layer to create the basic SOI CMOS structure. Particular modifications to the basic SOI CMOS structure include providing a mask for establishing ohmic contact with the wells below the buried oxide layer. The modification uses a separate mask which is generated from the existing bulk CMOS mask database.

Abstract: Apparatus and methods for determining the robustness of a device to soft errors generated by alpha-particle and/or cosmic ray strikes.

Abstract: A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. A clock signal defines a clock period with an active portion and a wait portion. The source region and/or the drain region are coupled to a body pumping signal. The body pumping signal includes a negative voltage pulse occurring during the wait portion which sets the voltage of a body region of the FET to a preset voltage during such negative voltage pulse. Decay of the preset voltage is predictable such that operation of the FET can be controlled during the active portion.

Abstract: A method and apparatus for controlling the growth of an oxide, such as a gate oxide, in a semiconductor device manufacturing process takes into consideration the ambient atmospheric pressure in order to reduce the variance in gate oxide thicknesses between wafer lots. The pressure in the oxide diffusion tube is maintained at a constant pressure near the ambient atmospheric pressure during the oxide diffusion process. Alternatively, the furnace time is changed from lot to lot as a function of changes in the ambient atmospheric pressure in order to maintain the gate oxide thickness at a constant value between wafer lots.

Abstract: Various embodiments of on chip-transformers constructed in separate metal layers in an insulator that serves as a dielectric which is formed on a substrate such as a silicon substrate. Windings with currents flowing in a first direction are constructed in a first metal layer and windings with currents flowing a second direction are constructed in a second metal layer. Windings in the first metal layer are connected to windings in the second metal layer by connectors such as vias. The transformer can be constructed in a balun layout, an autotransformer layout, a layout with the secondary separated from the primary, a layout with the secondary separated the primary and rotated with respect to an axis of the primary, a layout in which the transformer is a two stage transformer and with the first stage constructed orthogonal to the second stage, or a transformer in which the windings are constructed in a toroidal layout.

Abstract: A combination vertical MOSFET and JFET device (18,22) is formed in a mesa (20,24) of semiconductor material. A top gate (44,68) of the device is formed by creating a preferably annular trench (36,58) that extends downwardly from the surface of the semiconductor layer, creating a thin gate insulator (41,62) on the bottom and sidewalls of this trench, and filling the trench with highly doped polysilicon. A buried gate region (28,50) is formed by implanting the semiconductor layer, prior to top gate formation, such that the buried gate region is laterally coextensive with the mesa. An upper boundary (29,54) of the buried gate region is spaced below the bottom of the trench and spaced from the semiconductor surface. Upon application of a suitable voltage, the buried gate region and the top gate region coact to invert the conductivity type of the channel region, permitting transistor operation between the source region and the drain region.