Abstract: A method for navigating directly to defects on a blank wafer caused by particles dropped from process tools. A blank wafer is marked with fiducial marks, the number of initial defects on the blank wafer is determined and the position coordinates of the initial defects and the fiducial marks are recorded. The blank wafer is placed into a selected process tool and the additional defects that are caused by particles dropped from the process tool are detected in an inspection tool and their position coordinates are determined and recorded as well as the position coordinates of the fiducial marks. The blank wafer is then placed in an analysis tool that is able to navigate directly to each of the additional defects at a high magnification using the position coordinates of the fiducial marks.

Abstract: An arrangement that prevents triggering of latchup in internal circuits by input/output buffers on an integrated circuit chip provides a space surrounding each active device connected to a bond pad. A ring well surrounds the space and separates the active device from the internal circuits of the chip. The ring well serves as a collector to prevent triggering latchup by the active device of the internal circuits located outside the ring well.

Abstract: A method of manufacturing a raised source/drain MOSFET by depositing amorphous silicon on the partially formed MOSFET having the gate and gate oxide spacers formed, ion implanting to form the appropriate source/drain junctions, annealing wherein epitaxial growth takes place in regions where the amorphous silicon is over silicon, and etching the remaining amorphous silicon. A layer of refractory metal is deposited and a second anneal converts the refractory metal overlaying silicon to silicide.

Abstract: A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (L.sub.eff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom.

Abstract: A method of manufacturing a polysilicon plug in an integrated circuit semiconductor device wherein the polysilicon plug is selectively doped to act as a resistive load or alternatively to act as a diode load. The polysilicon load can be used in an SRAM memory cell.

Abstract: The electromigration lifetime of a metal interconnection line is increased by adjusting the length of the interconnection line, or providing longitudinally spaced apart holes or vias, to optimize the Backflow Potential Capacity of the metal interconnection line.

Abstract: The electromigration lifetime of a metal interconnection line is increased by adjusting the length of the interconnection line or providing longitudinally spaced apart holes or vias to optimize the backflow potential capacity of the metal interconnection line. In addition, elongated slots are formed through the metal interconnection line so that the total width of metal across the interconnection line is selected for optimum electromigration lifetime in accordance with the Bamboo Effect for that metal.

Abstract: High conductivity interconnection lines are formed of high conductivity material, such as copper, employing barrier layers impervious to the diffusion of copper atoms. Higher operating speeds are obtained with conductive interconnection lines, preferably copper interconnection lines, formed above the wire bonding layer.

Abstract: A low resistance interconnect structure for integrated circuits formed by a composite layer of aluminum below and an amorphous compound of refractory metal and silicon above. In the process of manufacturing the interconnect structure, care must be taken so that an aluminum oxide layer is not formed between the aluminum and compound layers.

Abstract: A method for making an integrated circuit structure having both PMOS and NMOS devices with lightly doped (LDD) source and drain regions is disclosed utilizing a single photoresist mask in which a substrate is implanted with a low concentration dopant of a first conductivity type through a silicon nitride shielding layer. Spacers are then formed against the sidewalls of oxide and nitride coated polysilicon gate electrodes by RIE etching of a polysilicon layer formed over the nitride shielding layer subsequent to the first implantation. A separate photoresist mask layer is then formed over a portion of the structure and the remaining exposed portions of the shielding nitride layer are then etched, resulting in the formation of first el-shaped shielding members against the sides of the gate electrodes.

Abstract: A semiconductor READ ONLY MEMORY (ROM) device is constructed by using a series of word lines as a mask during the fabrication of the underlying bit lines. The width of the word lines over each memory cell determines the characteristics of that cell (i.e. programmed or unprogrammed).

Abstract: A method for fabricating a complementary metal-oxide-silicon (CMOS) integrated circuit device by forming a composite layer of oxide and nitride on the surface of a silicon substrate defined into predetermined areas for the subsequent formation of transistors, masking the substrate to expose preselected areas for P-wells, ion implanting P-type material in the exposed areas to form P-wells so that a relatively high doping level is provided to a greater depth around composite areas within the P-wells areas and a relatively lower doping level is established under the composite layer areas with the P-wells. The ion implantation of P-type material may be accomplished in either a single stage or a two stage procedure.