Patents by Inventor Donald M. Kenney

Donald M. Kenney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020005533
    Abstract: A DRAM semiconductor device wherein a substrate plate trench (SPT) memory cell is formed in an N−-type substrate, without an epitaxial layer in which the substrate is biased at circuit ground in order to ensure that the substrate surrounding the trench capacitors is biased into accumulation in order to avoid unacceptable loss of storage node capacitance which would be caused by allowing the substrate to go into depletion.
    Type: Application
    Filed: December 30, 1998
    Publication date: January 17, 2002
    Inventors: DONALD M. KENNEY, PAUL C. PARRIES
  • Patent number: 5719080
    Abstract: A semiconductor trench capacitor structure having a first level aligned isolation structure and buried strap that extends from within the trench into the doped semiconductor substrate. The semiconductor trench capacitor structure may be fabricated by forming a shallow trench within the trench capacitor and semiconductor substrate, depositing a layer of conductive material within the shallow trench, using a mask to define and recess the strap and depositing insulating material within the shallow trench.
    Type: Grant
    Filed: August 31, 1995
    Date of Patent: February 17, 1998
    Assignee: International Business Machines Corporation
    Inventor: Donald M. Kenney
  • Patent number: 5710057
    Abstract: A first region of a seed substrate is separated from a bonded handle substrate by etching and/or fracturing a second region of the seed substrate. A third region of the seed substrate remains bonded to the handle wafer. Etching and etch ant distribution are facilitated by capillary action in trenches formed in the seed substrate prior to bonding of the handle substrate. A portion of the second region may be removed by undercut etching prior to handle bonding. Elevated pressure and etchant composition are used to suppress bubble formation during etching. Alternatively, pressure from bubble formation is used to fracture a portion of the second region. First, second, and third regions are defined by a variety of methods.
    Type: Grant
    Filed: July 12, 1996
    Date of Patent: January 20, 1998
    Inventor: Donald M. Kenney
  • Patent number: 5684314
    Abstract: An integrated structure is provided that includes a DRAM cell with a trench storage capacitor, and a corresponding storage node precharge circuit. The entire structure ideally requires only eight square features of area per memory bit. The structure also provides a partial leakage current shield for the DRAM storage node diffusion, thereby improving the data hold time. A graded impurity region around the storage node diffusion enhances the leakage shielding effect. The structure can be operated independently as a DRAM leakage shield if the precharge circuit is not needed. In that case, a junction diffusion in the structure can be eliminated and a leakage shielding effect is still achieved.
    Type: Grant
    Filed: March 18, 1996
    Date of Patent: November 4, 1997
    Inventor: Donald M. Kenney
  • Patent number: 5684313
    Abstract: A DRAM one device cell and an associated precharge circuit are integrated together in a novel structure having an area of only four square features. The structure also provides physical and electrical separation between adjacent cells along a direction parallel to the DRAM word lines. The DRAM bit line length per bit is reduced by 50% relative to a conventional planar integrated structure disclosed elsewhere. As a result, bit line capacitance is also substantially reduced, and the effectiveness of a precharge technique for reduction of DRAM power consumption is enhanced by the dense novel structure.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: November 4, 1997
    Inventor: Donald M. Kenney
  • Patent number: 5672537
    Abstract: Polysilicon (20) in a trench (21) is etched at an angle to produce a conductor within the trench that has shape characteristics which approximate the shadow of the side wall (26) of the trench (21) closest the beam source. Specifically, when the first side wall (26) is closest the beam source and the second side wall (27) is furthest from the beam source, the polysilicon on the first side wall (26) is almost as high as the first side wall (26), while the polysilicon on the more exposed side wall (27) is considerably lower than the first side wall (26) and approximates the shadow of the first side wall (26) on the second side wall (27) relative to the beam.
    Type: Grant
    Filed: September 17, 1996
    Date of Patent: September 30, 1997
    Assignee: International Business Machines Corporation
    Inventors: Daniel A. Carl, Donald M. Kenney, Walter E. Mlynko, Son Van Nguyen
  • Patent number: 5635419
    Abstract: The invention provides a capacitor structure utilizing porous silicon as a first plate of the capacitor structure, thereby greatly increasing the surface area available for the capacitor and thereby the capacitance attainable. The invention also provides a trench structure having a porous silicon region surrounding the sidewalls thereof. Such a trench can then be utilized to form a capacitor according to the subject invention. Methods of producing the capacitor and trench structures according to the subject invention are also provided. Porous silicon is produced utilizing electrolytic anodic etching.
    Type: Grant
    Filed: May 4, 1995
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Peter J. Geiss, Donald M. Kenney
  • Patent number: 5610441
    Abstract: Polysilicon in a trench is etched at an angle to produce a conductor within the trench that has shape characteristics which approximate the shadow of the side wall of the trench closest the beam source. Specifically, when the first side wall is closest to the beam source and the second side wall is furthest from the beam source, the polysilicon on the first side wall is almost as high as the first side wall, while the polysilicon on the more exposed side wall is considerably lower than the first side wall and approximates the shadow of the first side wall on the second side wall relative to the beam. The polysilicon in the trench may be in the shape of a solid angled block approximating the shadow line from the top of side wall to the shadow line on side wall however, it is preferred that the polysilicon take the form of a conformal layer in trench prior to etching such that the polysilicon ultimately has an angled "U" shape which approximates the shadow line.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: March 11, 1997
    Assignee: International Business Machines Corporation
    Inventors: Daniel A. Carl, Donald M. Kenney, Walter E. Mlynko, Son V. Nguyen
  • Patent number: 5583368
    Abstract: Chips having subsurface structures within or adjacent a horizontal trench in bulk single crystal semiconductor are presented. Structures include three terminal devices, such as FETs and bipolar transistors, rectifying contacts, such as pn diodes and Schottky diodes, capacitors, and contacts to and connectors between devices. FETs have low resistance connectors to diffusions while retaining low overlap capacitance. A low resistance and low capacitance contact to subsurface electrodes is achieved by using highly conductive subsurface connectors which may be isolated by low dielectric insulator. Stacks of devices are formed simultaneously within bulk single crystal semiconductor. A subsurface CMOS invertor is described. A process for forming a horizontal trench exclusively in heavily doped p+ regions is presented in which porous silicon is first formed in the p+ regions and then the porous silicon is etched.
    Type: Grant
    Filed: August 11, 1994
    Date of Patent: December 10, 1996
    Assignee: International Business Machines Corporation
    Inventor: Donald M. Kenney
  • Patent number: 5576566
    Abstract: A semiconductor trench capacitor structure having a first level aligned isolation structure and buried strap that extends from within the trench into the doped semiconductor substrate. The semiconductor trench capacitor structure may be fabricated by forming a shallow trench within the trench capacitor and semiconductor substrate, depositing a layer of conductive material within the shallow trench, using a mask to define and recess the strap and depositing insulating material within the shallow trench.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: November 19, 1996
    Assignee: International Business Machines Corporation
    Inventor: Donald M. Kenney
  • Patent number: 5532965
    Abstract: Performance is improved for a memory array composed of storage elements which require a preconditioning operation prior to writing new data or rewriting old data. At least one spare column of memory elements is provided. The spare column is preconditioned during a time when it is not used for data storage. During a write operation to a memory address, data are written into the preconditioned spare column instead of the column associated with the memory address. The memory address is reassociated with the spare column, and the column with which it was previously associated becomes a new spare column which is preconditioned during restore and made ready for use during a subsequent memory access. In this way time for the preconditioning operation is hidden, and no delay for preconditioning is incurred. A plurality of spare columns allows each spare column to be preconditioned during a plurality of memory cycles.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: July 2, 1996
    Inventor: Donald M. Kenney
  • Patent number: 5521118
    Abstract: The present invention is a sidewall connector providing a conductive path linking at least two conductive regions. The sidewall connector has a top portion comprising an outer surface. A conductive member contacts the top portion, connecting the rail to a conductive region or to an external conductor. An etch stop layer located on a conductive region can be used to protect the conductive region during the directional etch to form the sidewall connector. A conductive bridge is then used to link exposed portions of the conductive region and the conductive sidewall rail, the conductive bridge extending across the thickness of the etch stop layer. A "T" connector is formed by the process, starting with a pair of intersecting sidewalls wherein the two sidewalls have top edges at different heights where they intersect. The connector is used to form a strap for a DRAM cell.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: May 28, 1996
    Assignee: International Business Machines Corporation
    Inventors: Chung H. Lam, James S. Nakos, Donald M. Kenney, Eric Adler
  • Patent number: 5508542
    Abstract: The invention provides a capacitor structure utilizing porous silicon as a first plate of the capacitor structure, thereby greatly increasing the surface area available for the capacitor and thereby the capacitance attainable. The invention also provides a trench structure having a porous silicon region surrounding the sidewalks thereof. Such a trench can then be utilized to totem a capacitor according to the subject invention. Methods of producing the capacitor and trench structures according to the subject invention are also provided. Porous silicon is produced utilizing electrolytic anodic etching.
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: April 16, 1996
    Assignee: International Business Machines Corporation
    Inventors: Peter J. Geiss, Donald M. Kenney
  • Patent number: 5466636
    Abstract: A semiconductor fabrication process for forming borderless contacts (130, 170, 172) using a removable mandrel (110). The process involves depositing a mandrel on an underlying barrier layer (100) designed to protect underlying structures (40) formed on a substrate (24). The mandrel is made from a material that will etch at a faster rate than the barrier layer so as to permit the formation of openings in the mandrel to be stopped on the barrier layer without penetrating such layer. After depositing a contact (130) in a first opening (120) formed in the mandrel, a second opening (140) is formed and a second contact (170) is deposited therein. Thereafter, the mandrel is removed and replaced with a layer of solid dielectric material (180).
    Type: Grant
    Filed: September 17, 1992
    Date of Patent: November 14, 1995
    Assignee: International Business Machines Corporation
    Inventors: John E. Cronin, Carter W. Kaanta, Donald M. Kenney, Michael L. Kerbaugh, Howard S. Landis, Brian J. Machesney, Paul Parries, Rosemary A. Previti-Kelly, John F. Rembetski
  • Patent number: 5466626
    Abstract: The subject invention provides a method of forming recesses in a substrate such as a capacitor so as to increase the surface area thereof and therefore the charge storage capacity of the capacitor. This is accomplished by utilizing a micro mask formed by agglomeration on the surface of the substrate. The agglomerated material, such as gold, titanium nitride or titanium silicide, is used as a mask for selectively etching the substrate to form recesses therein. Alternatively, an oxide transfer mask can be utilized with the agglomerated material micro mask to etch the substrate.
    Type: Grant
    Filed: December 16, 1993
    Date of Patent: November 14, 1995
    Assignee: International Business Machines Corporation
    Inventors: Michael Armacost, A. Richard Baker, Jr., Wayne S. Berry, Daniel A. Carl, Donald M. Kenney, Thomas J. Licata
  • Patent number: 5414656
    Abstract: A dynamic random access memory is improved by a storage node precharge circuit so as to obtain both high stored voltage level and low charge consumption from a power supply. High voltage levels are written via the precharge circuit. Subsequently, low voltage levels are written via the access transistors and bit lines. As a result, the magnitude of the storage node voltage swing is independent of the magnitude of the bit line voltage swing. A given memory design may therefore be optimized independently for high stored voltage level and low bit line charge consumption.
    Type: Grant
    Filed: March 23, 1994
    Date of Patent: May 9, 1995
    Inventor: Donald M. Kenney
  • Patent number: 5412246
    Abstract: A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100 .ANG..
    Type: Grant
    Filed: January 26, 1994
    Date of Patent: May 2, 1995
    Assignee: International Business Machines Corporation
    Inventors: David M. Dobuzinsky, David L. Harmon, Srinandan R. Kasi, Donald M. Kenney, Son V. Nguyen, Tue Nguyen, Pai-Hung Pan
  • Patent number: 5399516
    Abstract: A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.
    Type: Grant
    Filed: September 21, 1992
    Date of Patent: March 21, 1995
    Assignee: International Business Machines Corporation
    Inventors: Albert S. Bergendahl, Claude L. Bertin, John E. Cronin, Howard L. Kalter, Donald M. Kenney, Chung H. Lam, Hsing-San Lee
  • Patent number: 5384281
    Abstract: A process for etching narrow features, particularly submicron borderless contacts, in a semiconductor substrate is disclosed. The process comprises depositing, by an orientation-sensitive technique, film which will act as an etch stop. The film is significantly thicker on horizontal surfaces than on vertical. A second layer is deposited and then etched using the first film as an etch stop. In one embodiment the etch stop is composed of an oxidizable material.
    Type: Grant
    Filed: December 29, 1992
    Date of Patent: January 24, 1995
    Assignee: International Business Machines Corporation
    Inventors: Donald M. Kenney, Stephen E. Luce
  • Patent number: 5365097
    Abstract: Vertical epitaxial SOI transistors and memory cells are disclosed. The devices are formed completely within a substrate trench and have a bulk channel epitaxially grown on an exposed surface of the substrate within the trench. The bulk channel is disposed proximate to a transistor gate electrode such that an inversion layer is formed therein when the gate electrode is appropriately biased. Back biasing of the bulk region is accomplished through the substrate. In the transistor embodiment, a first node diffusion and a second node diffusion are disposed at opposite ends of the bulk channel. In a memory cell configuration the access transistor is disposed above a trench storage node, which electrically connects with the transistor's second node diffusion. Arrays of the trench transistors and trench memory cells are also described. Further, fabrication methods for the various structures disclosed are presented. A novel wiring approach to construction of bit lines in a cell array is also set forth.
    Type: Grant
    Filed: October 5, 1992
    Date of Patent: November 15, 1994
    Assignee: International Business Machines Corporation
    Inventor: Donald M. Kenney