Patents by Inventor Donald M. Kenney
Donald M. Kenney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5360758Abstract: A deep trench type DRAM cell with shallow trench isolation has a buried polysilicon strap that is defined without the use of a separate mask by depositing the strap material over at least the deep trench before shallow trench definition and using the shallow trench isolation mask to overlap partially the deep trench, thereby defining the strap during the process of cutting the shallow trench.Type: GrantFiled: December 3, 1993Date of Patent: November 1, 1994Assignee: International Business Machines CorporationInventors: Gary B. Bronner, John K. DeBrosse, Donald M. Kenney
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Patent number: 5348905Abstract: A high density substrate plate DRAM cell memory device and process are described in which a buried plate region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried region is partially formed by lateral outdiffusion from the sidewalls of the deep trenches and partially formed by an N-well surface diffusion which entirely surrounds the DRAM array region.Type: GrantFiled: August 26, 1993Date of Patent: September 20, 1994Assignee: International Business Machines CorporationInventor: Donald M. Kenney
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Patent number: 5330935Abstract: A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100.ANG..Type: GrantFiled: July 21, 1992Date of Patent: July 19, 1994Assignee: International Business Machines CorporationInventors: David M. Dobuzinsky, David L. Harmon, Srinandan R Kasi, Donald M. Kenney, Son Van Nguyen, Tue Nguyen, Pai-Hung Pan
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Patent number: 5264716Abstract: A high density substrate plate DRAM cell memory device is described in which a buried plate region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried region is partially formed by lateral outdiffusion from the sidewalls of the deep trenches and partially formed by an N-well surface diffusion which entirely surrounds the DRAM array region.Type: GrantFiled: January 9, 1992Date of Patent: November 23, 1993Assignee: International Business Machines CorporationInventor: Donald M. Kenney
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Patent number: 5254503Abstract: A method is provided to enable the formation of sub-lithographic relief images to increase the surface area of semiconductor structures for use in the storage nodes of DRAM cells. The method includes the steps of forming in situ a non-planar region having a relief pattern comprising sub-micron sized elements and the transferring the relief pattern into a masking layer in order to selectively etch a substrate to form relatively deep trenches having a density equal to the relief pattern. Polysilicon and porous silicon can be used to form the sub-micron relief pattern.Type: GrantFiled: June 2, 1992Date of Patent: October 19, 1993Assignee: International Business Machines CorporationInventor: Donald M. Kenney
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Patent number: 5196722Abstract: A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.Type: GrantFiled: March 12, 1992Date of Patent: March 23, 1993Assignee: International Business Machines CorporationInventors: Albert S. Bergendahl, Claude L. Bertin, John E. Cronin, Howard L. Kalter, Donald M. Kenney, Chung H. Lam, Hsing-San Lee
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Patent number: 5001525Abstract: A very small memory cell utilizing only two squares at a major surface is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, a storage capacitor having a storage node disposed within a given sidewall of the trench, a switching device coupled to the storage capacitor and having an elongated current carrying element disposed within the given sidewall with its longitudinal direction arranged parallel to that of the longitudinal axis of the trench and a control element disposed on the sidewall of the trench between the storage capacitor and the elongated current carrying element, and an electrically conductive line disposed on the major surface of the semiconductor substrate in a direction orthogonal to the longitudinal axis of the trench and in contact with the control element of the switching device.Type: GrantFiled: March 27, 1989Date of Patent: March 19, 1991Assignee: International Business Machines CorporationInventor: Donald M. Kenney
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Patent number: 4970689Abstract: A gain memory cell circuit includes a storage capacitor connected between a storage node and ground, a write word line, a read word line, a second capacitor capactively coupling the read word line to the storage node, a read transistor having its source/drain path coupled between the bit line and ground and having its gate coupled to the storage node, and a write transistor having its source/drain path coupled between the storage node and bit line and a control electrode connected to the write word line.Type: GrantFiled: February 26, 1990Date of Patent: November 13, 1990Assignee: International Business Machines CorporationInventor: Donald M. Kenney
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Patent number: 4939567Abstract: A sub-surface interconnection structure for coupling an n-type diffusion to a p-type diffusion. The structure is a conductor-filled trench disposed between the diffusion regions. The trench has a thin dielectric layer on its sidewalls and bottom. The conductor within the trench contacts the diffusion regions. Parasitic device formation between the diffusion regions is suppressed because the trench provides a parasitic gate that is shorted to the parasitic source regions (i.e., the coupled diffusion regions). Moreover, the trench provides an enlarged contact to the coupled diffusion regions for the subsequently-applied metal layer.Type: GrantFiled: January 30, 1989Date of Patent: July 3, 1990Assignee: IBM CorporationInventor: Donald M. Kenney
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Patent number: 4914740Abstract: A charge amplifying memory cell and its memory of making based on trench technology. A trench is formed which reaches through an n-type well region to a p.sup.+ -type substrate. A triple layer is formed on two sidewalls of the trench consisting of two capacitive insulating layers and a intermediate p.sup.+ polysilicon layer. The trench is then at least partially filled with a conductor, such as polysilicon, facing the triple layer. Thereby, the intermediate polysilicon layer acts as a charge storage node with capacitance to both the substrate and the polysilicon filling the trench. The insulating layer facing the well is opened with a contact hole near its top so that a p.sup.+ transistor drain is formed in the adjacent well by diffusion from the polysilicon through the contact hole. A p.sup.+ transistor source is doped into the well with a gate region between it and the drain to provide a write transistor.Type: GrantFiled: March 7, 1988Date of Patent: April 3, 1990Assignee: International Business CorporationInventor: Donald M. Kenney
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Patent number: 4838991Abstract: A conformal organic layer is used to define spacers on the sidewalls of an organic mandrel. The organic layer (e.g., parylene) can be deposited at low temperatures, and as such is compatible with temperature-sensitive mandrel materials that reflow at high deposition temperatures. The conformal organic material can be dry etched as the same rate as the organic mandrels, while being resistant to wet strip solvents that remove the organic mandrels. This series of etch characteristics make the organic mandrel-organic spacer combination compatible with a host of masking applications.Type: GrantFiled: June 20, 1988Date of Patent: June 13, 1989Assignee: International Business Machines CorporationInventors: William J. Cote, Donald M. Kenney, Michael L. Kerbaugh, Michael A. Leach, Jeffrey A. Robinson, Robert W. Sweetser
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Patent number: 4833094Abstract: A one-device shared trench memory cell, in which the polysilicon and dielectric layers within the trench extend above the surface of the trench to form a mandrel structure. A layer of polysilicon is conformably deposited on the mandrel structure. Dopant ions are diffused from the doped polysilicon within the trench to the conformal polysilicon layer, and from the conformal polysilicon layer, and from the conformal polysilicon layer to a portion of the substrate disposed thereunder. The conformal polysilicon is etched in a solvent that preferentially attacks undoped polysilicon, to provide and is a bridge contact that is self-aligned to the polysilicon within the trench and to the diffusion region. A plurality of FETs formed on either side of the trench, by use of a sidewall-defined gate electrode to maximize density. The cell produces a "poly-to-poly" and "poly-to-substrate" storage capacitor combination that maximizes charge storage capability.Type: GrantFiled: August 29, 1988Date of Patent: May 23, 1989Assignee: International Business Machines CorporationInventor: Donald M. Kenney
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Patent number: 4801988Abstract: A semiconductor trench capacitor construction having a self-aligned isolation structure formed within the trench. The trench isolation structure consists of a thick isolating layer formed along the upper portion of the trench side walls. The trench isolation structure facilitates larger capacitor constructions and allows the capacitors to abut adjacent capacitors and other devices.Type: GrantFiled: October 31, 1986Date of Patent: January 31, 1989Assignee: International Business Machines CorporationInventor: Donald M. Kenney
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Patent number: 4785337Abstract: A one-device shared trench memory cell, in which the polysilicon and dielectric layers within the trench extend above the surface of the trench to form a mandrel structure. A layer of polysilicon is conformably deposited on the mandrel structure. Dopant ions are diffused from the doped polysilicon within the trench to the conformal polysilicon layer, and from the conformal polysilicon layer, and from the conformal polysilicon layer to a portion of the substrate disposed thereunder. The conformal polysilicon is etched in a solvent that preferentially attacks undoped polysilicon, to provide and is a bridge contact that is self-aligned to the polysilicon within the trench and to the diffusion region. A plurality of FETs formed on either side of the trench, by use of a sidewall-defined gate electrode to maximize density. The cell produces a "poly-to-poly" and "poly-to-substrate" storage capacitor combination that maximizes charge storage capability.Type: GrantFiled: October 17, 1986Date of Patent: November 15, 1988Assignee: International Business Machines CorporationInventor: Donald M. Kenney
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Patent number: 4769786Abstract: A memory is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, storage means disposed on a given sidewall of the trench, switching means having a control element and a current carrying element disposed on the given sidewall of the trench between the storage means and the major surface of the substrate and coupled to the storage means, a first electrically conductive line disposed on the given sidewall in contact with the control element of the switching means and having a longitudinal axis arranged parallel to the longitudinal axis of the trench, and a second electrically conductive line disposed on the major surface of the semiconductor substrate in contact with the current carrying electrode of the switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of the trench.Type: GrantFiled: July 15, 1986Date of Patent: September 6, 1988Assignee: International Business Machines CorporationInventors: Richard R. Garnache, Donald M. Kenney
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Patent number: 4751558Abstract: A memory cell formed in a groove or trench in a semiconductor substrate is provided which includes a storage capacitor located at the bottom and along the lower portion of the sidewalls of the trench, a bit/sense line disposed at the surface of the semiconductor substrate adjacent to the trench, a transfer device or transistor located on the sidewall of the trench between the capacitor and the bit/sense line and a field shield for electrically isolating the storage capacitor from an adjacent cell formed in the same semiconductor substrate.Type: GrantFiled: October 31, 1985Date of Patent: June 14, 1988Assignee: International Business Machines CorporationInventor: Donald M. Kenney
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Patent number: 4648073Abstract: A memory array is provided which includes a common sense line to which is connected first and second series of cells, each cell of each series includes a storage capacitor, a switching device and a bit line connected to a plate of the storage capacitor, with a common word line connected to the control electrode of each of the switching devices. The switching devices, preferably field effect transistors, of each series of cells have progressively higher threshold voltages beginning at the sense line, and the voltage applied to the common word line has a magnitude greater than that of the highest threshold voltage. Data is stored into or read from the storage capacitors by selecting the common word line and the bit line of the desired cell in a sequential manner.Type: GrantFiled: December 31, 1984Date of Patent: March 3, 1987Assignee: International Business Machines CorporationInventor: Donald M. Kenney
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Patent number: 4642491Abstract: A driver circuit is provided which includes a field effect transistor having first and second spaced apart semiconductor regions of a given conductivity type and a third semiconductor region of a conductivity type opposite to the given conductivity type interposed between the first and second regions and having a given sustaining voltage serially connected with a capacitor. The circuit further includes means for applying between the first and second spaced apart regions a given supply voltage having a magnitude greater than the magnitude of the sustaining voltage and less than the breakdown voltage of a PN junction formed in the transistor and means including a control voltage applied to the gate electrode of the transistor for initiating current flow between the first and second spaced apart regions when the given supply voltage is applied between the first and second spaced apart regions.Type: GrantFiled: June 24, 1983Date of Patent: February 10, 1987Assignee: International Business Machines CorporationInventors: Donald M. Kenney, Jack A. Mandelman
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Patent number: 4511911Abstract: A dynamic memory is provided having a cell with an improved structure and made by an improved process which substantially reduces the capacitance of the bit/sense line connected to the cell. The cell has one field effect transistor and a storage node, and the cell structure includes a thick insulating segment located under a portion of a conductive layer or field shield and under a portion of the gate electrode of the transistor, while extending over the entire diffusion region of the bit/sense line and over substantially the entire depletion region surrounding the bit/sense line diffusion region.Type: GrantFiled: July 22, 1981Date of Patent: April 16, 1985Assignee: International Business Machines CorporationInventor: Donald M. Kenney
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Patent number: RE33972Abstract: A memory is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, storage means disposed on a given sidewall of the trench, switching means having a control element and a current carrying element disposed on the given sidewall of the trench between the storage means and the major surface of the substrate and coupled to the storage means, a first electrically conductive line disposed on the given sidewall in contact with the control element of the switching means and having a longitudinal axis arranged parallel to the longitudinal axis of the trench, and a second electrically conductive line disposed on the major surface of the semiconductor substrate in contact with the current carrying electrode of the switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of the trench.Type: GrantFiled: October 30, 1990Date of Patent: June 23, 1992Assignee: International Business Machines CorporationInventors: Richard R. Garnache, Donald M. Kenney