Abstract: Disclosed are a pixel, a pixel array, an image sensor including the pixel array and a method for operating the image sensor. The pixel includes a photo-electro conversion unit; a first capacitor for storing a first quantity of charges of the photo-electro conversion unit; a second capacitor for storing a second quantity of charges of the photo-electro conversion unit; and an output unit to output the first and second quantities of the charges.

Abstract: A head unit fixed sewing machine is provided, which includes a table, support posts, an upper beam, a head unit and a bed unit. An object is placed on the table. The support posts are provided on opposite sides of the table. The upper beam connects the support posts to each other and is coupled to upper ends of the support posts. The head unit is fastened to the upper beam and has a head-unit-rotating means for rotating a sewing head within a predetermined range. The bed unit is provided below the head unit and has a bed-unit-rotating means for rotating a sewing bed within a predetermined range. Because the head unit and the bed unit can be rotated while sewing, the orientation of a sewn thread can be maintained constant. Hence, a perfect stitch can be realized over the entirety of the object.

Abstract: A sewing machine is provided, which includes a table, support posts, upper and lower frames, a head unit, a bed unit, an X-axial head-unit-transport means and an X-axial bed-unit-transport means. An object is placed on the table. The support posts are provided on opposite sides of the table. The upper and lower frames connect the support posts to each other. The head unit is provided on the upper frame so as to be movable in an X-axis direction. The head unit has a head-unit-rotating means for rotating a sewing head. The bed unit is provided on the lower frame so as to be movable in the X-axis direction. The bed unit has a bed-unit-rotating means for rotating a sewing bed. The X-axial head-unit-transport means moves the head unit on the upper frame horizontally. The X-axial bed-unit-transport means moves the bed unit on the upper frame horizontally.

Abstract: Disclosed herein is a lead pin for a package substrate. The lead pin for the package substrate includes a cylindrical connection pin; and a head part that is formed on one end of the connection pin and has a convex round part formed on the lower end of the head part, having a step part. When the lead pin for the package substrate is mounted on the package substrate, the bulge phenomenon of a solder paste that surrounds the head part and is melted is prevented by a flange part, thereby making it possible to prevent the connection pin from being polluted and to improve a contact defect such as a short defect or the like when coupling a socket.

Abstract: Disclosed herein is a Fourier transform-based phasor estimation method and apparatus capable of eliminating the influence of exponentially decaying DC offsets. According to a Fourier transform-based phasor estimation method according to an embodiment of the present invention, an input signal is sampled, and samples of one-cycle data of the input signal are separated into at least two sample groups. A Discrete Fourier Transform (DFT) is performed on each of the sample groups. A DC offset included in the input signal is calculated on a basis of results of the DFT on each of the sample groups, and an error caused by the DC offset is calculated using the calculated DC offset. A phasor of a fundamental frequency component included in the input signal is estimated by eliminating the calculated error, caused by the DC offset, from the results of the DFT on the input signal.

Abstract: There is provided a package substrate capable of controlling the degree of warpage thereof by improving the composition and formation of a post terminal and a method of fabricating the same. The package substrate includes a substrate having at least one conductive pad; an insulating layer provided on the substrate and having an opening to expose the conductive pad; a separation barrier layer provided on the conductive pad inside the opening and formed to be higher than the upper surface of the insulating layer along the side walls thereof; a post terminal provided on the separation barrier layer; and a solder bump provided on the post terminal.

Abstract: There is provided a package substrate allowing for enhanced reliability by improving the structure of a solder bump and a method of fabricating the same. The package substrate includes: a substrate having at least one conductive pad; an insulating layer provided on the substrate and having an opening to expose the conductive pad; a post terminal provided on the conductive pad inside the opening; and a solder bump provided on the post terminal and having an angle between a bottom surface and a side surface thereof ranging from 80° to 120°.

Abstract: There is provided a method of manufacturing a substrate for flip chip, and a substrate for flip chip manufactured using the same. The method includes providing a base substrate including at least one conductive pad, forming a solder resist layer on the base substrate, the solder resist layer including a first opening exposing the conductive pad, forming a dry film on the solder resist layer, the dry film including a second opening connected with the first opening, forming a metal post in the first opening and a part of the second opening, filling the second opening above the metal post with solder paste, forming a solder cap by performing a reflow process on the filled solder paste, planarizing a surface of the solder cap, and removing the dry film. Accordingly, fine pitches and improve reliability can be achieved.

Abstract: Disclosed herein is a lead pin for a package substrate. The lead pin for the package substrate includes a cylindrical connection pin; and a head part that is formed on one end of the connection pin and has a convex round part formed on the lower end of the head part, having a step part. When the lead pin for the package substrate is mounted on the package substrate, the bulge phenomenon of a solder paste that surrounds the head part and is melted is prevented by a flange part, thereby making it possible to prevent the connection pin from being polluted and to improve a contact defect such as a short defect or the like when coupling a socket.

Abstract: Disclosed is a substrate for flip chip bonding, in which a base solder layer is formed between a pad and a metal post, thereby increasing impact resistance and mounting reliability. A method of fabricating the substrate for flip chip bonding is also provided.

Abstract: The present invention relates to a thermal exchange device using heat pipes to effectively discharge heat from inside of an open-air communication system. The present invention provides a plurality of heat pipes directly inserted between the plates of the thermo-electric cooling unit for accommodating a plurality of fins thereon. According to the structure suggested by the invention, since the heat pipes can be placed laterally with the thermo-electric cooling unit, the size of the overall communication system can be reduced with the same discharge capability.

Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. In accordance with an embodiment of the present invention, the method includes providing a substrate having a pad formed thereon, forming a resist on the substrate, in which the resist has an opening formed therein such that the pad is exposed, forming a metal post inside the opening such that the metal post is electrically connected to the pad, forming a through-hole in the resist by removing a portion of the resist such that the through-hole surrounds the metal post, and forming a solder layer inside the through-hole and on an upper surface of the metal post so as to cover an exposed surface of the metal post.

Abstract: Non-restoring radix-2 division and square rooting procedures are provided. The proposed procedures utilize a quotient/root digit set {?1, 0, +1} and a quotient/root prediction table (QRT/RPT). The i'th quotient/root digit is determined with reference to a partial remainder from (i?2)'th iterative operation and by the quotient/root prediction table. The present procedures generate the (i?1)'th correction term, which is to be applied in calculating the i'th partial remainder, simultaneously with the (i?2)'th correction term, and need not to perform an iterative operation to obtain the i'th partial remainder.

Abstract: A method of driving a display panel includes; sensing an illumination of a surrounding area which surrounds the display panel, and selectively displaying a black line image on the display panel in accordance with the illumination of the surrounding area.

Abstract: A wafer packaging method is disclosed. An aspect of the invention is to provide a wafer packaging method comprising; attaching tape onto one side of a carrier, the carrier having a through-hole formed therein; attaching a wafer onto the tape exposed inside the through-hole such that at least one electrode of the wafer is exposed; and performing a packaging process on the carrier such that the wafer is packaged.

Abstract: The invention relates to a substrate having a metal post and a method of manufacturing the same, in which a round solder bump part formed on a metal post melts and flows down along a lateral surface of the metal post by being subjected twice to a reflow process, thus forming a solder bump film for preventing oxidation and corrosion of the metal post.

Abstract: Provided is a printed circuit board (PCB) including a substrate that has a pad formed thereon; solder resist that is disposed on the substrate so as to expose the pad; a post that is disposed on the post; a surface-treatment layer that is disposed on the post; and a bump that is disposed on the surface-treatment layer.

Abstract: Disclosed herein is a Fourier transform-based phasor estimation method and apparatus capable of eliminating the S influence of exponentially decaying DC offsets. According to a Fourier transform-based phasor estimation method according to an embodiment of the present invention, an input signal is sampled, and samples of one-cycle data of the input signal are separated into at least two sample groups. A Discrete Fourier Transform (DFT) is performed on each of the sample groups. A DC offset included in the input signal is calculated on a basis of results of the DFT on each of the sample groups, and an error caused by the DC offset is calculated using the calculated DC offset. A phasor of a fundamental frequency component included in the input signal is estimated by eliminating the calculated error, caused by the DC offset, from the results of the DFT on the input signal.

Abstract: A programmable logic array (PLA) which may include an AND-plane receiving first input signals and generating logic product signals based on the first input signals, and an OR-plane receiving the logic product signals and a second input signal and generating a logic sum signal based on the logic product signals.

Abstract: A printed circuit board for use in a package and to a method of manufacturing the printed circuit board. The method of manufacturing the printed circuit board can include: providing a substrate, on one side of which at least one solder pad and at least one guide pad are formed; forming a solder resist layer over the one side of the substrate; uncovering at least one portion of the solder resist layer such that the guide pad is exposed; applying a surface treatment on the exposed guide pad; uncovering at least one portion of the solder resist layer such that the solder pad is exposed; and forming a solder bump on the exposed solder pad. With this method, the amount of surface treatment applied can be minimized, for reduced costs, and the occurrence of undiffused layers can be avoided, for improved reliability in the final product.