Abstract: A computing system is provided. The computing system includes: a memory configured to store a shader program; and a graphics processing unit (GPU) configured to obtain the shader program stored in the memory in a profile mode, the GPU being configured to perform: inserting, into the shader program, one or more monitor associative codes; compiling the shader program, into which the one or more monitor associative codes are inserted, into a language that is capable of being processed by a plurality of cores; and obtaining a runtime performance characteristic of the shader program by executing the compiled shader program and the one or more monitor associative codes.

Abstract: An apparatus configured to render an object including a path includes a storage circuit, an arithmetic circuit configured to determine a direction of a plurality of primitives included in the path based on path data, generate primitive direction information, store the primitive direction information in the storage circuit, and generate a winding number of each of a plurality of pixels using the stored primitive direction information, and a determination circuit configured to determine whether a shading operation is to be performed based on the generated winding number.

Abstract: A multi-core computing device includes a control core group having first low-level control cores and a processing core group. The control core group allocates work groups for executing an Open Computing Language (OpenCL) kernel to the first low-level control cores and first processing cores among the processing core group. The processing core group performs processing of the work groups allocated by the control core group outputs results of the processing. The control cores are hierarchically grouped.

Abstract: Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.

Abstract: Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.

Abstract: A processor device includes a scheduler and a performance counter. The scheduler schedules commands of a first command set and commands of a second command set for a functional unit. A performance counter counts numbers of times where events of interest respectively occur while the functional unit processes first operations directed by the first command set and second operations directed by the second command set. The commands of the first command set are repeatedly scheduled such that the numbers of times for all the events of interest are counted with regard to the first operations. The commands of the second command set are scheduled after the numbers of times for all the events of interest are counted with regard to the first operations.

Abstract: A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations.

Abstract: A method of processing data including receiving data to be stored in a first group of cache banks from among a plurality of cache banks corresponding to a plurality of cores. The method further includes partitioning the received data and transmitting the partitioned data to the first group of cache banks according to a write intensity of the received data, and storing a portion of the transmitted data in a first cache bank from among the first group of cache banks.

Abstract: Provided are a graphics processing unit and a graphics processing method for performing path rendering. The graphics processing method may include receiving object information including primitive information regarding the object; generating a primitive mask with respect to respective pixels, the primitive mask corresponding to the primitive information and including a plurality of bits; generating, based on the primitive mask, winding numbers with respect to the respective pixels; and rendering the pixels, based on the winding numbers.

Abstract: Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.

Abstract: A multi-core computing device includes a control core group having first low-level control cores and a processing core group. The control core group allocates work groups for executing an Open Computing Language (OpenCL) kernel to the first low-level control cores and first processing cores among the processing core group. The processing core group performs processing of the work groups allocated by the control core group outputs results of the processing. The control cores are hierarchically grouped.

Abstract: A method of processing data including receiving data to be stored in a first group of cache banks from among a plurality of cache banks corresponding to a plurality of cores. The method further includes partitioning the received data and transmitting the partitioned data to the first group of cache banks according to a write intensity of the received data, and storing a portion of the transmitted data in a first cache bank from among the first group of cache banks.

Abstract: The present examples relate to prefetching, and to a cache control device for prefetching and a prefetching method using the cache control device, wherein the cache control device analyzes a memory access pattern of program code, inserts, into the program code, a prefetching command generated by encoding the analyzed access pattern, and executes the prefetching command inserted into the program code in order to prefetch data into a cache, thereby maximizing prefetching efficiency.

Abstract: Provided are an apparatus and method for providing instructions for a heterogeneous processor having heterogeneous components supporting different data widths. Respective data widths of operands and connections in a data flow graph are determined by using type information of operands. Instructions, to be executed by the heterogeneous processor, are provided based on the determined data widths.

Abstract: A method and apparatus for translating a multithread program code are provided. The method includes: dividing a multithread program code into a plurality of statements according to a synchronization point; generating at least one loop group by combining one or more adjacent statements based on a number of instructions included in the plurality of statements; expanding or renaming variables in each of the plurality of statements so that each statement included in the at least one loop group is executed with respect to a work item of a different work group; and enclosing each of the generated at least one loop group respectively with a work item coalescing loop.

Abstract: A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.

Abstract: A technology for executing an external operation from a software-pipelined loop is provided. Code performance efficiency can be improved by overlapping the execution of the external operations of the loop and the iterations of the loop.

Abstract: An apparatus and method for generating vector code are provided. The apparatus and method generate vector code using scalar-type kernel code, without user's changing a code type or modifying data layout, thereby enhancing user's convenience of use and retaining the portability of OpenCL.

Abstract: An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein. The VLIW command includes an instruction bundle formed of a plurality of instructions to be executed in parallel and a single value indicating predicated execution, and is generated using the apparatus and method for generating a VLIW command. The VLIW processor decodes the instruction bundle and executes the instructions, which are included in the decoded instruction bundle, in parallel, according to the value indicating predicated execution.

Abstract: An instruction compressing apparatus and method for a parallel processing computer such as a very long instruction word (VLIW) computer, are provided. The instruction compressing apparatus includes a bundle code generating unit, an instruction compressing unit, and an instruction converting unit. The bundle code generating unit may generate a bundle code in response to an input of instructions to be compressed. The bundle code may indicate whether a current instruction group is terminated, and also whether an instruction group following the current instruction group is a no-operation (NOP) instruction group. The instruction compressing unit may remove a NOP instruction and/or a NOP instruction group from the input instructions according to the generated bundle code. The instruction converting unit may include the generated bundle code in the remaining instructions which have not been removed by the instruction compressing unit.