Abstract: A memory managing apparatus and method are provided. The memory managing apparatus may determine, based on a pointer indicator bit, the target memory area on which garbage collection is to be performed, and may perform the garbage collection on the target memory area. The memory managing apparatus may generate the pointer indicator bit and store the generated pointer indicator bit in a pointer field.

Abstract: Provided is a technique for improving the transfer latency of vector register file data when an interrupt is generated. According to an aspect, when interrupt occurs, a core determines whether to store vector register file data currently being executed in a first memory or in a second memory based on whether or not the first memory can store the vector register file data therein. In response to not being able to store the vector register file data in the first memory, a data transfer unit, which is implemented as hardware, is provided to store vector register file data in the second memory.

Abstract: An interrupt support determining apparatus and method for an equal-model processor, and a processor including the interrupt support determining apparatus are provided. The interrupt support determining apparatus determines whether an instruction input to a processor decoder is a multiple latency instruction, compares a current latency of the instruction with a remaining latency if the instruction is a multiple latency instruction, and updates the current latency to the remaining latency if the current latency is greater than the remaining latency.

Abstract: A computing apparatus and method of handling an interrupt are provided. The computing apparatus includes a coarse-grained array, a host processor, and an interrupt supervisor. When an interrupt occurs in the coarse-grained array while performing a loop operation, the host processor processes the interrupt, and the interrupt supervisor may perform mode switching between the coarse-grained array and the host processor.

Abstract: A profiler which provides information to optimize an application specific architecture processor and a program for the processor is provided.

Abstract: A technology for executing an external operation from a software-pipelined loop is provided. Code performance efficiency can be improved by overlapping the execution of the external operations of the loop and the iterations of the loop.

Abstract: An interrupt handling technology and a reconfigurable processor are provided. The reconfigurable processor includes a plurality of processing elements, and some of the processing elements are designated for interrupt handling. When an interrupt request occurs while the reconfigurable processor is executing a loop operation, the designated processing elements may process the interrupt request. The interrupt handling technology allows the interrupt request and the loop operation to be processed in parallel.

Abstract: A swizzle pattern generator is provided to reduce an overhead due to execution of a swizzle instruction in vector processing. The swizzle pattern generator is configured to provide swizzle patterns with respect to data sets of at least one vector register or vector processing unit. The swizzle pattern generator may be reconfigurable to generate various swizzle patterns for different vector operations.

Abstract: A format conversion apparatus which converts image data of a band interleave format into image data of a band separate format is provided. The apparatus includes a memory which stores image data of a band interleave format; and a converting module which reads the memory by increasing a read address of the memory for each stride, and converts the image data of the band interleave format into image data of a band separate format.

Abstract: Provided is an apparatus and method capable of processing code to which a software pipelining is not applicable, in a CGA mode. The apparatus may include a processing unit that has a very long instruction word (VLIW) mode and a coarse-grained array (CGA) mode, and an adjusting unit configured to detect a target region to which software pipelining is not applicable, in code to be executed by the processing unit. The adjusting unit may selectively map the detected target region to one of the VLIW mode and the CGA mode according to a schedule length of the detected target region.

Abstract: An apparatus and method for compressing trace data is provided. The apparatus includes a detection unit configured to detect trace data corresponding to one or more function units performing a substantially significant operation in a reconfigurable processor as valid trace data, and a compression unit configured to compress the valid trace data.

Abstract: A register file is provided. The register file includes a plurality of registers configured to form at least one register cluster, each of the registers being configured to have a virtual index defined for each cluster and a physical index defined for each register, and an index converting unit configured to convert the virtual index to the physical index.

Abstract: A method and apparatus for thread synchronization is provided. The apparatus for thread synchronization includes a reader configured to generate a data read request, a writer configured to generate a data write request, a register file configured to have a full status indicating that the register file stores data and an empty status indicating that the register file stores no data, and a controller configured to receive the data read request from the reader or the data write request from the writer, and to process the received data read request or the received data write request while stalling or releasing the reader or the writer according to whether the register file is in the full status or in the empty status and according to an operating status of the reader or the writer.

Abstract: An apparatus and method for dynamically determining the execution mode of a reconfigurable array are provided. Performance information of a loop may be obtained before and/or during the execution of the loop. The performance information may be used to determine whether to operate the apparatus in a very long instruction word (VLIW) mode or in a coarse grained array (CGA) mode.

Abstract: A reconfigurable processor which merges an inner loop and an outer loop which are included in a nested loop and allocates the merged loop to processing elements in parallel, thereby reducing processing time to process the nested loop. The reconfigurable processor may extract loop execution frequency information from the inner loop and the outer loop of the nested loop, and may merge the inner loop and the outer loop based on the extracted loop execution frequency information.

Abstract: Provided are a reconfigurable processor, which is capable of reducing the probability of an incorrect computation by analyzing the dependence between memory access instructions and allocating the memory access instructions between a plurality of processing elements (PEs) based on the results of the analysis, and a method of controlling the reconfigurable processor. The reconfigurable processor extracts an execution trace from simulation results, and analyzes the memory dependence between instructions included in different iterations based on parts of the execution trace of memory access instructions.

Abstract: A technology for reducing pipeline a control hazard is provided. A conditional branch is processed through a conditional branch prediction, and a predetermined conditional branch prediction, which is determined as incorrect, may be modified through a following test for the conditional branch prediction, thereby reducing the pipeline control hazard quickly without additional hardware.

Abstract: Provided are a computing apparatus based on a reconfigurable architecture and a memory dependence correction method thereof. In one general aspect, a computing apparatus has a reconfigurable architecture. The computing apparatus may include: a reconfiguration unit having processing elements configured to reconfigure data paths between one or more of the processing elements; a compiler configured to analyze instructions to generate reconfiguration information for reconfiguring one or more of the reconfigurable data paths; a configuration memory configured to store the reconfiguration information; and a processor configured to execute the instructions through the reconfiguration unit, and to correct at least one memory dependency among the processing elements.

Abstract: A debugging apparatus and method are provided. The debugging apparatus may include a breakpoint setting unit configured to store a first instruction corresponding to a breakpoint in a table, stop a program currently being executed, and insert a breakpoint instruction including current location information of the first instruction into the breakpoint; and an instruction execution unit configured to selectively execute one of the breakpoint instruction and the first instruction according to a value of a status bit.

Abstract: An apparatus and method that includes a single memory as a VLIW instruction cache and CGA configuration memory is provided. Data is provided from a storage unit to a processing core that is capable of processing data in a first mode and a second mode. If the processing core is processing in the first mode, first data is output. If the processing core is processing in the second mode, second data is output.