Patents by Inventor Dong Hyeon Jang
Dong Hyeon Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240075620Abstract: A functional safety system of a robot according to an exemplary embodiment of the present disclosure can generate a safety zone which is a zone to sense whether an obstacle is present.Type: ApplicationFiled: May 12, 2023Publication date: March 7, 2024Inventors: Seong Ju PARK, Dong Hyeon SEO, Seung Ho JANG, Min Chang, Yun Jib Kim, Chang Woo Kim
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Publication number: 20240077618Abstract: A functional safety system of a robot according to an exemplary embodiment of the present disclosure can duplicate modules so as to satisfy a performance level d (pl-d) required for the functional satisfy of a robot.Type: ApplicationFiled: May 12, 2023Publication date: March 7, 2024Inventors: Seong Ju PARK, Dong Hyeon SEO, Seung Ho JANG, Min Chang, Yun Jib Kim, Chang Woo Kim
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Publication number: 20240075622Abstract: A functional safety system of a robot according to an exemplary embodiment of the present disclosure can duplicate modules so as to satisfy a performance level d (pl-d) required for the functional satisfy of a robot.Type: ApplicationFiled: May 12, 2023Publication date: March 7, 2024Inventors: Seong Ju PARK, Dong Hyeon SEO, Seung Ho JANG, Min Chang, Yun Jib Kim, Chang Woo Kim
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Patent number: 11663954Abstract: A display device includes a substrate including a display area and a peripheral area disposed around the display area, a pad area disposed near an edge of the substrate, and a plurality of pads disposed in the pad area and arranged along the edge of the substrate. An end of a first pad, which is an outermost pad among the plurality of pads, is connected to a first end of a resistor. The first pad is disposed between the resistor and the edge of the substrate, and a second end of the resistor is connected to a wire.Type: GrantFiled: December 6, 2021Date of Patent: May 30, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Young-Soo Yoon, Yun-Kyeong In, Su Kyoung Kim, Won Se Lee, Dong Hyeon Jang, Yu-Jin Jeon, Hyun Ji Cha
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Patent number: 11616116Abstract: A display device includes a display panel that has a display area displaying an image and a non-display area around the display area. The display panel includes: a substrate; a plurality of connection lines on the substrate in the non-display area and including a first connection line and a second connection line adjacent to each other; a first dummy line overlapping and disposed on the first connection line; and a second dummy line overlapping the second connection line and disposed between the substrate and the second connection line.Type: GrantFiled: July 2, 2020Date of Patent: March 28, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Yu-Jin Jeon, Dae Suk Kim, Jun-Yong An, Won Se Lee, Dong Hyeon Jang
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Publication number: 20220093033Abstract: A display device includes a substrate including a display area and a peripheral area disposed around the display area, a pad area disposed near an edge of the substrate, and a plurality of pads disposed in the pad area and arranged along the edge of the substrate. An end of a first pad, which is an outermost pad among the plurality of pads, is connected to a first end of a resistor. The first pad is disposed between the resistor and the edge of the substrate, and a second end of the resistor is connected to a wire.Type: ApplicationFiled: December 6, 2021Publication date: March 24, 2022Inventors: Young-Soo Yoon, Yun-Kyeong In, Su Kyoung Kim, Won Se Lee, Dong Hyeon Jang, Yu-Jin Jeon, Hyun Ji Cha
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Patent number: 11195449Abstract: A display device includes a substrate including a display area and a peripheral area disposed around the display area, a pad area disposed near an edge of the substrate, and a plurality of pads disposed in the pad area and arranged along the edge of the substrate. An end of a first pad, which is an outermost pad among the plurality of pads, is connected to a first end of a resistor. The first pad is disposed between the resistor and the edge of the substrate, and a second end of the resistor is connected to a wire.Type: GrantFiled: June 26, 2020Date of Patent: December 7, 2021Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Young-Soo Yoon, Yun-Kyeong In, Su Kyoung Kim, Won Se Lee, Dong Hyeon Jang, Yu-Jin Jeon, Hyun Ji Cha
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Patent number: 11031347Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.Type: GrantFiled: April 11, 2019Date of Patent: June 8, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Young-lyong Kim, Hyun-soo Chung, Dong-hyeon Jang
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Publication number: 20210097928Abstract: A display device includes a substrate including a display area and a peripheral area disposed around the display area, a pad area disposed near an edge of the substrate, and a plurality of pads disposed in the pad area and arranged along the edge of the substrate. An end of a first pad, which is an outermost pad among the plurality of pads, is connected to a first end of a resistor. The first pad is disposed between the resistor and the edge of the substrate, and a second end of the resistor is connected to a wire.Type: ApplicationFiled: June 26, 2020Publication date: April 1, 2021Inventors: Young-Soo YOON, Yun-Kyeong IN, Su Kyoung KIM, Won Se LEE, Dong Hyeon JANG, Yu-Jin JEON, Hyun Ji CHA
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Publication number: 20210005704Abstract: A display device includes a display panel that has a display area displaying an image and a non-display area around the display area. The display panel includes: a substrate; a plurality of connection lines on the substrate in the non-display area and including a first connection line and a second connection line adjacent to each other; a first dummy line overlapping and disposed on the first connection line; and a second dummy line overlapping the second connection line and disposed between the substrate and the second connection line.Type: ApplicationFiled: July 2, 2020Publication date: January 7, 2021Inventors: Yu-Jin JEON, Dae Suk KIM, Jun-Yong AN, Won Se LEE, Dong Hyeon JANG
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Patent number: 10438899Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.Type: GrantFiled: January 12, 2018Date of Patent: October 8, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Young-lyong Kim, Hyun-soo Chung, Dong-hyeon Jang
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Publication number: 20190237410Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.Type: ApplicationFiled: April 11, 2019Publication date: August 1, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Young-lyong KIM, Hyun-soo Chung, Dong-hyeon Jang
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Publication number: 20190051612Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.Type: ApplicationFiled: January 12, 2018Publication date: February 14, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Iyong KIM, Hyun-soo CHUNG, Dong-hyeon JANG
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Patent number: 9941196Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.Type: GrantFiled: April 15, 2016Date of Patent: April 10, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho-Jin Lee, Tae-Je Cho, Dong-Hyeon Jang, Ho-Geon Song, Se-Young Jeong, Un-Byoung Kang, Min-Seung Yoon
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Publication number: 20160233155Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.Type: ApplicationFiled: April 15, 2016Publication date: August 11, 2016Inventors: Ho-Jin LEE, Tae-Je CHO, Dong-Hyeon JANG, Ho-Geon SONG, Se-Young JEONG, Un-Byoung KANG, Min-Seung YOON
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Patent number: 9343361Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.Type: GrantFiled: November 5, 2013Date of Patent: May 17, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho-Jin Lee, Tae-Je Cho, Dong-Hyeon Jang, Ho-Geon Song, Se-Young Jeong, Un-Byoung Kang, Min-Seung Yoon
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Patent number: 9245827Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.Type: GrantFiled: April 25, 2014Date of Patent: January 26, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Uk-song Kang, Dong-hyeon Jang, Seong-jin Jang, Hoon Lee, Jin-ho Kim, Nam-seog Kim, Byung-sik Moon, Woo-dong Lee
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Patent number: 9136260Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.Type: GrantFiled: December 2, 2013Date of Patent: September 15, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-seok Ahn, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im, Chang-seong Jeon, Teak-hoon Lee, Sang-sick Park
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Publication number: 20140233292Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.Type: ApplicationFiled: April 25, 2014Publication date: August 21, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Uk-song Kang, Dong-hyeon Jang, Seong-jin Jang, Hoon Lee, Jin-ho Kim, Nam-seog Kim, Byung-sik Moon, Woo-dong Lee
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Publication number: 20140154839Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.Type: ApplicationFiled: December 2, 2013Publication date: June 5, 2014Inventors: Jung-seok Ahn, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im, Chang-seong Jeon, Teak-hoon Lee, Sang-sick Park