Abstract: According to the disclosure, a display device includes a substrate including a display area and a non-display area, outer pixels positioned in the display area and positioned in a first direction from an edge of the substrate, dummy holes positioned in the non-display area and positioned between the edge of the substrate and the outer pixels, and a dummy line positioned in the non-display area and extending in a second direction different from the first direction between the dummy holes. The dummy line is positioned between a first insulating layer and a second insulating layer, and the dummy holes pass through the first insulating layer and the second insulating layer.

Abstract: A display device includes: a substrate; a pixel electrode on the substrate; a bank on the pixel electrode, and defining an emission area; a first transistor connected to the pixel electrode; and a driving electrode connected to the first transistor, and including: a main electrode extended in a direction; and a sub-electrode branching off from the main electrode. At least one of the main electrode or the sub-electrode overlaps with the emission area to divide the emission area into at least two sub-emission areas in a plan view.

Abstract: A display device includes a substrate including a display area and a peripheral area disposed around the display area, a pad area disposed near an edge of the substrate, and a plurality of pads disposed in the pad area and arranged along the edge of the substrate. An end of a first pad, which is an outermost pad among the plurality of pads, is connected to a first end of a resistor. The first pad is disposed between the resistor and the edge of the substrate, and a second end of the resistor is connected to a wire.

Abstract: A display device includes a display panel that has a display area displaying an image and a non-display area around the display area. The display panel includes: a substrate; a plurality of connection lines on the substrate in the non-display area and including a first connection line and a second connection line adjacent to each other; a first dummy line overlapping and disposed on the first connection line; and a second dummy line overlapping the second connection line and disposed between the substrate and the second connection line.

Abstract: A display device includes a substrate including a display area and a peripheral area disposed around the display area, a pad area disposed near an edge of the substrate, and a plurality of pads disposed in the pad area and arranged along the edge of the substrate. An end of a first pad, which is an outermost pad among the plurality of pads, is connected to a first end of a resistor. The first pad is disposed between the resistor and the edge of the substrate, and a second end of the resistor is connected to a wire.

Abstract: A display device includes a substrate including a display area and a peripheral area disposed around the display area, a pad area disposed near an edge of the substrate, and a plurality of pads disposed in the pad area and arranged along the edge of the substrate. An end of a first pad, which is an outermost pad among the plurality of pads, is connected to a first end of a resistor. The first pad is disposed between the resistor and the edge of the substrate, and a second end of the resistor is connected to a wire.

Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.

Abstract: A display device includes a substrate including a display area and a peripheral area disposed around the display area, a pad area disposed near an edge of the substrate, and a plurality of pads disposed in the pad area and arranged along the edge of the substrate. An end of a first pad, which is an outermost pad among the plurality of pads, is connected to a first end of a resistor. The first pad is disposed between the resistor and the edge of the substrate, and a second end of the resistor is connected to a wire.

Abstract: A display device includes a display panel that has a display area displaying an image and a non-display area around the display area. The display panel includes: a substrate; a plurality of connection lines on the substrate in the non-display area and including a first connection line and a second connection line adjacent to each other; a first dummy line overlapping and disposed on the first connection line; and a second dummy line overlapping the second connection line and disposed between the substrate and the second connection line.

Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.

Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.

Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.