Patents by Inventor Dong-hyun Roh

Dong-hyun Roh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955531
    Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: April 9, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-young Kwak, Ji-ye Kim, Jung-hwan Chun, Min-chan Gwak, Dong-hyun Roh, Jin-wook Lee, Sang-jin Hyun
  • Publication number: 20240014209
    Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.
    Type: Application
    Filed: September 25, 2023
    Publication date: January 11, 2024
    Inventors: Gyu-Hwan Ahn, Sung-Soo Kim, Chae-Ho Na, Dong-Hyun Roh, Sang-Jin Hyun
  • Patent number: 11804483
    Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: October 31, 2023
    Inventors: Gyu-Hwan Ahn, Sung-Soo Kim, Chae-Ho Na, Dong-Hyun Roh, Sang-Jin Hyun
  • Patent number: 11728409
    Abstract: A semiconductor device includes first and second active patterns each extending in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction. A field insulating layer is disposed between the first active pattern and the second active pattern. A first gate structure is disposed on the first active pattern and extends in the second direction. An interlayer insulating layer is disposed between the first gate structure and the field insulating layer. The interlayer insulating layer includes a first part disposed below the first gate structure. A spacer is disposed between the first gate structure and the first part of the interlayer insulating layer.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: August 15, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun Hye Lee, Sung Soo Kim, Ik Soo Kim, Woong Sik Nam, Dong Hyun Roh
  • Publication number: 20230233502
    Abstract: The present invention relates to a novel cocrystal, a pharmaceutical composition comprising same and a preparation method therefor. By using the cocrystal of the present invention, cancers, inflammatory diseases, or viral infection diseases may be effectively prevented and/or treated.
    Type: Application
    Filed: January 28, 2022
    Publication date: July 27, 2023
    Inventors: Young Joon PARK, Sook CHOI, Ga Haeng LEE, Dong Hyun ROH
  • Publication number: 20230207662
    Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.
    Type: Application
    Filed: February 27, 2023
    Publication date: June 29, 2023
    Inventors: Dae-young KWAK, Ji -ye KIM, Jung-hwan CHUN, Min-chan GWAK, Dong-hyun ROH, Jin-wook LEE, Sang-jin HYUN
  • Patent number: 11626503
    Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: April 11, 2023
    Inventors: Dae-young Kwak, Ji-ye Kim, Jung-hwan Chun, Min-chan Gwak, Dong-hyun Roh, Jin-wook Lee, Sang-jin Hyun
  • Patent number: 11600518
    Abstract: A semiconductor device includes a substrate having first fin and a second fin spaced apart and extending lengthwise in parallel. A fin remnant is disposed between the first fin and the second fin, extends lengthwise in parallel with the first and second fins, and has a height lower than a height of each of the first fin and the second fin. A first field insulation layer is disposed between a sidewall of the first fin and a first sidewall of the fin remnant and a second field insulating layer is disposed on a sidewall of the second fin. A blocking liner conforms to a sidewall and a bottom surface of a trench bounded by a second sidewall of the fin remnant and a sidewall of the second field insulating layer. A trench insulation layer is disposed on the blocking liner in the trench.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: March 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Soo Kim, Chae Ho Na, Gyu Hwan Ahn, Dong Hyun Roh, Sang Jin Hyun
  • Publication number: 20220393030
    Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a first fin-type pattern and a second fin-type pattern on a substrate, a first epitaxial pattern on the first fin-type pattern, a second epitaxial pattern on the second fin-type pattern, and a lower field insulating film on the substrate and extends on a sidewall of the first fin-type pattern and a sidewall of the second fin-type pattern, wherein the lower field insulating film includes a protrusion protruding in a third direction. The protrusion of the lower field insulating film may be between the first fin-type pattern and the second fin-type pattern, and a vertical level of a top surface of the protrusion of the lower field insulating film increases and then decreases with increasing distance from the sidewall of the first fin-type pattern.
    Type: Application
    Filed: February 9, 2022
    Publication date: December 8, 2022
    Inventors: Chae Ho NA, Sung Soo Kim, Sun Ki Min, Dong Hyun Roh
  • Patent number: 11495223
    Abstract: An electronic device according to various embodiments may comprise a memory in which one or more applications are installed, a communication circuit, and a processor, wherein the processor is configured to acquire audio data during execution of a designated application among the one or more applications, wherein the acquiring of audio data comprises an operation of storing, in the memory, at least a portion including multiple pieces of phoneme information among the audio data, when a designated condition is satisfied, transmit the at least portion to an external electronic device so that the external electronic device generates designated information for execution of at least one application among the one or more applications by using at least a part of the multiple pieces of phoneme information stored before the designated condition is satisfied, and on the basis of the designated information, execute the at least one application in relation to the designated application.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: November 8, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Gi Ahn, Joo Yoo Kim, Ji Eun Kim, Dong Hyun Roh, Kyung Sub Min, Seung Eun Lee
  • Publication number: 20220262673
    Abstract: A semiconductor device includes a substrate, a first fin, and a second fin. The first and second fins are spaced apart from each other in a first direction on the substrate and extend in a second direction intersecting the first direction. The semiconductor device further includes a first shallow trench formed between the first and second fins, and a field insulating film which fills at least a part of the first shallow trench. The field insulating film includes a first portion, a second portion adjacent to the first portion, and a third portion adjacent to the second portion and adjacent to a side wall of the first shallow trench. The first portion includes a central portion of an upper surface of the field insulating film in the first direction. The upper surface of the field insulating film is in a shape of a brace recessed toward the substrate.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Inventors: Chae Ho NA, Sung Soo KIM, Gyu Hwan AHN, Dong Hyun ROH
  • Patent number: 11416213
    Abstract: An electronic device includes a microphone, a processor, and a memory. The memory stores an application for monitoring user information, and the memory stores instructions that, when executed by the processor, cause the electronic device to record a plurality of parameters associated with the user information in the application when a predefined event occurs to record a first parameter and the first parameter is not recorded in the application, to output a message for obtaining the first parameter, to receive a user response associated with the first parameter, to transmit data associated with the user response to an external server, to receive a first response from the external server, and to record the first parameter in the application by allowing the electronic device to have information about sequences of states of the electronic device. The first response includes information about sequences of states of the electronic device for recording the first parameter in the application.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: August 16, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo Yoo Kim, Jun Hui Kim, Ji Eun Kim, Tae Ho Kim, Dong Hyun Roh, Hyun Gi Ahn, Da Som Lee, Seung Eun Lee
  • Patent number: 11328949
    Abstract: A semiconductor device includes a substrate, a first fin, and a second fin. The first and second fins are spaced apart from each other in a first direction on the substrate and extend in a second direction intersecting the first direction. The semiconductor device further includes a first shallow trench formed between the first and second fins, and a field insulating film which fills at least a part of the first shallow trench. The field insulating film includes a first portion, a second portion adjacent to the first portion, and a third portion adjacent to the second portion and adjacent to a side wall of the first shallow trench. The first portion includes a central portion of an upper surface of the field insulating film in the first direction. The upper surface of the field insulating film is in a shape of a brace recessed toward the substrate.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: May 10, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chae Ho Na, Sung Soo Kim, Gyu Hwan Ahn, Dong Hyun Roh
  • Publication number: 20220069092
    Abstract: A semiconductor device may include first and second fin-shaped patterns on a substrate, that extend in a first direction, and are spaced apart from each other in a second direction. A first epitaxial pattern may be on the first fin-shaped pattern, and a second epitaxial pattern may be on the second fin-shaped pattern. A field insulating layer may be on the substrate, and may cover a sidewall of the first fin-shaped pattern, a sidewall of the second fin-shaped pattern, a part of a sidewall of the first epitaxial pattern, and a part of a sidewall of the second epitaxial pattern. The top surface of the field insulating layer may be higher than the bottom surface of the first epitaxial pattern and the bottom surface of the second epitaxial pattern.
    Type: Application
    Filed: March 30, 2021
    Publication date: March 3, 2022
    Inventors: Sun Ki Min, Chae Ho Na, Sang Koo Kang, Ik Soo Kim, Dong Hyun Roh
  • Patent number: 11217343
    Abstract: An electronic device includes a sensor, a processor, and a memory configured to store at least one instruction executed by the processor, wherein the processor is configured to collect activity information on a user related to the electronic device by using the sensor, the collecting of the activity information including creating an amount of activity of the user for a specific goal or an activity engagement level for the specific goal by using the activity information, adjust at least one of an output time point, an output cycle, the number of outputs, or the output contents of the activity guide information for the user to an activity guide parameter at least based on the amount of activity or the activity engagement level, and output the activity guide information created by using the adjusted activity guide parameter through an output device operatively connected to the processor.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: January 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: No Ah Lee, Dong Geon Kim, Kwang Yuel Ryu, Chung Ki Lee, David Rim, Min Hee Jang, Pravinsagar Prabakaran, Dong Hyun Roh, Jae Woong Chun
  • Publication number: 20210384321
    Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.
    Type: Application
    Filed: August 3, 2021
    Publication date: December 9, 2021
    Inventors: Dae-young KWAK, Ji -ye KIM, Jung-hwan CHUN, Min-chan GWAK, Dong-hyun ROH, Jin-wook LEE, Sang-jin HYUN
  • Publication number: 20210328039
    Abstract: A semiconductor device includes first and second active patterns each extending in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction. A field insulating layer is disposed between the first active pattern and the second active pattern. A first gate structure is disposed on the first active pattern and extends in the second direction. An interlayer insulating layer is disposed between the first gate structure and the field insulating layer. The interlayer insulating layer includes a first part disposed below the first gate structure. A spacer is disposed between the first gate structure and the first part of the interlayer insulating layer.
    Type: Application
    Filed: December 4, 2020
    Publication date: October 21, 2021
    Inventors: Sun Hye LEE, Sung Soo KIM, Ik Soo KIM, Woong Sik NAM, Dong Hyun ROH
  • Patent number: 11114544
    Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: September 7, 2021
    Inventors: Dae-young Kwak, Ji-ye Kim, Jung-hwan Chun, Min-chan Gwak, Dong-hyun Roh, Jin-wook Lee, Sang-jin Hyun
  • Publication number: 20210257250
    Abstract: A semiconductor device includes a substrate having first fin and a second fin spaced apart and extending lengthwise in parallel. A fin remnant is disposed between the first fin and the second fin, extends lengthwise in parallel with the first and second fins, and has a height lower than a height of each of the first fin and the second fin. A first field insulation layer is disposed between a sidewall of the first fin and a first sidewall of the fin remnant and a second field insulating layer is disposed on a sidewall of the second fin. A blocking liner conforms to a sidewall and a bottom surface of a trench bounded by a second sidewall of the fin remnant and a sidewall of the second field insulating layer. A trench insulation layer is disposed on the blocking liner in the trench.
    Type: Application
    Filed: May 5, 2021
    Publication date: August 19, 2021
    Inventors: Sung Soo KIM, Chae Ho NA, Gyu Hwan AHN, Dong Hyun ROH, Sang Jin HYUN
  • Publication number: 20210193656
    Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.
    Type: Application
    Filed: February 17, 2021
    Publication date: June 24, 2021
    Inventors: Gyu-Hwan Ahn, Sung-Soo Kim, Chae-Ho Na, Dong-Hyun Roh, Sang-Jin Hyun