Abstract: A resistance variable memory device may include a plurality of tiles in which memory cells are arranged. The first to third level of the word lines may be sequentially stacked on the plurality of tile regions with the decoding circuits along rows of the tile regions. A first level of the bit lines may be interposed between the first level of the word lines and the second level of the word lines. A first level of the bit lines may be extended along columns of the tile regions. The second level of the bit lines may be interposed between the second level of the word lines and the third level of the word lines. The second level of the bit lines may be extended along the columns of the tile regions. The first and third levels of the word lines at a selected row of a selected tile region among the tile regions and the second level of the bit lines at a selected column of the selected tile region may be controlled by a decoding circuit of the selected tile region.

Abstract: A resistance variable memory device may include a plurality of tiles in which memory cells are arranged. The first to third level of the word lines may be sequentially stacked on the plurality of tile regions with the decoding circuits along rows of the tile regions. A first level of the bit lines may be interposed between the first level of the word lines and the second level of the word lines. A first level of the bit lines may be extended along columns of the tile regions. The second level of the bit lines may be interposed between the second level of the word lines and the third level of the word lines. The second level of the bit lines may be extended along the columns of the tile regions. The first and third levels of the word lines at a selected row of a selected tile region among the tile regions and the second level of the bit lines at a selected column of the selected tile region may be controlled by a decoding circuit of the selected tile region.

Abstract: A resistance variable memory device may include a plurality of tiles in which memory cells are arranged. The first to third level of the word lines may be sequentially stacked on the plurality of tile regions with the decoding circuits along rows of the tile regions. A first level of the bit lines may be interposed between the first level of the word lines and the second level of the word lines. A first level of the bit lines may be extended along columns of the tile regions. The second level of the bit lines may be interposed between the second level of the word lines and the third level of the word lines. The second level of the bit lines may be extended along the columns of the tile regions. The first and third levels of the word lines at a selected row of a selected tile region among the tile regions and the second level of the bit lines at a selected column of the selected tile region may be controlled by a decoding circuit of the selected tile region.

Abstract: A semiconductor memory apparatus may include a memory bank, a global buffer array, and an input and output circuit. The memory bank includes a local data circuit, and the global buffer array includes a global data circuit. The local data circuit is operably coupled to the global data circuit. The global buffer array may be operably coupled to the input and output circuit. The memory bank is disposed in a core region, and the global buffer array and the input and output circuit may be disposed in a peripheral region separated from the core region.

Abstract: A circuit board for a power supply, an electronic apparatus including the same, and an inductor device are provided. The circuit board includes a first pattern arranged on a first layer of the circuit board and including a first terminal coupled to a coil, a first layer region arranged on the first layer, the coil being disposed on the first layer region, and a second pattern arranged on a second layer of the circuit board, below the first layer. The second pattern includes a first blank region located below the first layer region, and has no conductive material arranged thereon.

Abstract: Described is a smart lighting method and device. A smart lighting control method comprises the steps of: operating a smart bulb, which includes a control unit for controlling at least one lighting attribute among attributes of saturation, brightness, and color-temperature, and an LED lamp operated by the control unit; acquiring a current attribute of the LED lamp by using a smartwatch communicatably connected with the control unit; selecting an attribute to be controlled, through an interface panel of the smartwatch; obtaining a control attribute value for adjusting the lighting attribute, by using a rotation interface of the smartwatch; and transmitting the control attribute value from the smartwatch to the smart bulb and adjusting a lighting attribute of the smart bulb by using the transmitted control attribute value.

Abstract: A semiconductor apparatus may include a repair circuit configured to activate a redundant line of a cell array region by comparing repair information and address information. The semiconductor apparatus may include a main decoder configured to perform a normal access to the cell array region by decoding the address information. The address information may include both column information and row information.

Abstract: Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit including one or more column, a data line, and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns may include a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and a second variable resistance elements; a bit line connected to one end of the first variable resistance element; a bit line bar connected to one end of the second variable resistance element; a source line connected to the other ends of the first and second variable resistance elements; and a driving block configured to latch data of the data line and the data line bar.

Abstract: The present invention provides a steering apparatus for a vehicle, the apparatus including: a plate bracket supported on distance brackets and having a first slot through which an adjustment bolt passes, the distance brackets being coupled to the outer circumferential surface of an upper tube to face each other; a stationary gear coupled to the plate bracket, wherein the stationary gear has a second slot that corresponds to the first slot and through which the adjustment bolt passes and first gear teeth formed at opposite edges thereof; and a movable gear having a through-hole through which adjustment bolt passes and second gear teeth formed on opposite sides thereof and engaged with the first gear teeth.

Abstract: Described is a smart lighting method and device. A smart lighting control method comprises the steps of: operating a smart bulb, which includes a control unit for controlling at least one lighting attribute among attributes of saturation, brightness, and color-temperature, and an LED lamp operated by the control unit; acquiring a current attribute of the LED lamp by using a smartwatch communicatably connected with the control unit; selecting an attribute to be controlled, through an interface panel of the smartwatch; obtaining a control attribute value for adjusting the lighting attribute, by using a rotation interface of the smartwatch; and transmitting the control attribute value from the smartwatch to the smart bulb and adjusting a lighting attribute of the smart bulb by using the transmitted control attribute value.

Abstract: Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit comprising one or more columns and a date line and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns includes a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and second variable resistance elements; a bit line and a source line connected to the first variable resistance element; connected to the other end of the first variable resistance element; a bit line bar and a source line bar connected to the second variable resistance element; and a driving block configured to latch data of the data line and the data line bar.

Abstract: A data sense amplifier may include: first and second external nodes, wherein a potential difference occurs between the first and second external nodes when a memory cell is selected; an amplification unit suitable for generating and amplifying a potential difference between first and second nodes in response to the potential difference between the first and second external nodes; and a switching unit suitable for electrically coupling the first and second external nodes to the first and second nodes, respectively, after a predetermined time elapses from when the memory cell is selected.

Abstract: Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit including one or more column, a data line, and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns may include a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and a second variable resistance elements; a bit line connected to one end of the first variable resistance element; a bit line bar connected to one end of the second variable resistance element; a source line connected to the other ends of the first and second variable resistance elements; and a driving block configured to latch data of the data line and the data line bar.

Abstract: An electronic device includes a semiconductor memory device. The semiconductor memory device includes: a word line driving unit for driving a plurality of word lines; a first circuit area including a first cell array arranged at one side of the word line driving unit; a second circuit area including a second cell array arranged at the other side of the word line driving unit; a bias voltage generation unit arranged between the first cell array and the second cell array; a first read control unit; and a second read control unit. The first and second cell arrays include storage cells having variable resistance elements, and the bias voltage generation unit generates a bias voltage based on currents flowing through a first reference resistance element included in the first cell array and a second reference resistance element included in the second cell array.

Abstract: Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit including one or more column, a data line, and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns may include a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and a second variable resistance elements; a bit line connected to one end of the first variable resistance element; a bit line bar connected to one end of the second variable resistance element; a source line connected to the other ends of the first and second variable resistance elements; and a driving block configured to latch data of the data line and the data line bar.

Abstract: The present invention provides a steering apparatus for a vehicle, the apparatus including: a plate bracket supported on distance brackets and having a first slot through which an adjustment bolt passes, the distance brackets being coupled to the outer circumferential surface of an upper tube to face each other; a stationary gear coupled to the plate bracket, wherein the stationary gear has a second slot that corresponds to the first slot and through which the adjustment bolt passes and first gear teeth formed at opposite edges thereof; and a movable gear having a through-hole through which adjustment bolt passes and second gear teeth formed on opposite sides thereof and engaged with the first gear teeth.

Abstract: According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.

Abstract: Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit comprising one or more columns and a date line and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns includes a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and second variable resistance elements; a bit line and a source line connected to the first variable resistance element; connected to the other end of the first variable resistance element; a bit line bar and a source line bar connected to the second variable resistance element; and a driving block configured to latch data of the data line and the data line bar.

Abstract: A sense amplifier includes an equalization unit configured to precharge a pair of bit lines to a level of a bit line precharge voltage in response to a bit line equalizing signal; and an amplification unit configured to sense and amplify voltages of the pair of bit lines, supply, during an active operation, a ground voltage to a pull-down node of a latch section, and supply, when a precharge signal is enabled, a first voltage lower than the ground voltage to the pull-down node of the latch section for a predetermined time.

Abstract: A circuit board for a power supply, an electronic apparatus including the same, and an inductor device are provided. The circuit board includes a first pattern arranged on a first layer of the circuit board and including a first terminal coupled to a coil, a first layer region arranged on the first layer, the coil being disposed on the first layer region, and a second pattern arranged on a second layer of the circuit board, below the first layer. The second pattern includes a first blank region located below the first layer region, and has no conductive material arranged thereon.