Patents by Inventor Dong-Seog Eun

Dong-Seog Eun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10964720
    Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 30, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Kim, Kwang Young Jung, Dong Seog Eun
  • Publication number: 20210028190
    Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 28, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jong Won KIM, Kwang Young JUNG, Dong Seog EUN
  • Patent number: 10886289
    Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: January 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shin-hwan Kang, Young-hwan Son, Dong-seog Eun, Chang-sup Lee, Jae-hoon Jang
  • Patent number: 10854631
    Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: December 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Kim, Kwang Young Jung, Dong Seog Eun
  • Publication number: 20200135761
    Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 30, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jong Won KIM, Kwang Young JUNG, Dong Seog EUN
  • Patent number: 10546874
    Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: January 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Kim, Kwang Young Jung, Dong Seog Eun
  • Patent number: 10396092
    Abstract: Disclosed are vertical memory devices and methods of manufacturing the same. The vertical memory device may include includes a substrate, a gate stack structure and channel structure on the substrate, and a charge trap structure between the gate stack structure and the channel structure. The gate stack structure includes conductive structures and insulation interlayer structures that are alternately stacked on each other in a vertical direction on the substrate such that cell regions and inter-cell regions are alternately arranged in the vertical direction. The channel structure penetrates through the gate stack structure in the vertical direction. The charge trap structure and the conductive structures define memory cells at the cell regions. The charge structure is configured to selectively store charges. The charge trap structure includes an anti-coupling structure in the inter-cell region for reducing a coupling between neighboring memory cells adjacent to each other in the vertical direction.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: August 27, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kohji Kanamori, Dong-Seog Eun
  • Publication number: 20190115366
    Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 18, 2019
    Inventors: BYOUNG IL LEE, Joong Shik Shin, Dong Seog Eun, Kyung Jun Shin, Hyun Kook Lee
  • Patent number: 10211220
    Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung Il Lee, Kyung Jun Shin, Dong Seog Eun, Ji Hye Kim, Hyun Kook Lee
  • Patent number: 10204919
    Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung Il Lee, Joong Shik Shin, Dong Seog Eun, Kyung Jun Shin, Hyun Kook Lee
  • Patent number: 10153292
    Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Kim, Seung Hyun Lim, Chang Seok Kang, Young Woo Park, Dae Hoon Bae, Dong Seog Eun, Woo Sung Lee, Jae Duk Lee, Jae Woo Lim, Hanmei Choi
  • Publication number: 20180350831
    Abstract: A semiconductor memory device including a substrate including a first block and a second block each having a cell array region and a connection region, a stack including insulating layers and gate electrodes and extending from the cell array region to the connection region, first cell channel structures in the cell array region of the first block and passing through the stack to be electrically connected to the substrate, first dummy channel structures in the connection region of the first block and passing through the stack, second cell channel structures in the cell array region of the second block and passing through the stack, and second dummy channel structures in the connection region of the second block and passing through the stack may be provided. The first dummy channel structures are electrically insulated from the substrate, while the second dummy channel structures are electrically connected to the substrate.
    Type: Application
    Filed: December 14, 2017
    Publication date: December 6, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Kim, Kwang Young Jung, Dong Seog EUN
  • Patent number: 10103165
    Abstract: A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of vertical holes extending in a direction perpendicular to the upper surface of the substrate to penetrate through the gate structure, and a plurality of vertical structures in the plurality of vertical holes, respectively, each vertical structure of the plurality of vertical structures including an embedded insulating layer, and a plurality of channel layers separated from each other, the plurality of channel layers being outside the embedded insulating layer.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 16, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Hwan Son, Won Chul Jang, Dong Seog Eun, Jae Hoon Jang
  • Publication number: 20180226423
    Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.
    Type: Application
    Filed: April 5, 2018
    Publication date: August 9, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Shin-hwan KANG, Young-hwan SON, Dong-seog EUN, Chang-sup LEE, Jae-hoon JANG
  • Publication number: 20180190668
    Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
    Type: Application
    Filed: February 28, 2018
    Publication date: July 5, 2018
    Inventors: JONG WON KIM, SEUNG HYUN LIM, CHANG SEOK KANG, YOUNG WOO PARK, DAE HOON BAE, DONG SEOG EUN, WOO SUNG LEE, JAE DUK LEE, JAE WOO LIM, HANMEI CHOI
  • Patent number: 9991271
    Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: June 5, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shin-hwan Kang, Young-hwan Son, Dong-seog Eun, Chang-sup Lee, Jae-hoon Jang
  • Patent number: 9972636
    Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: May 15, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Kim, Seung Hyun Lim, Chang Seok Kang, Young Woo Park, Dae Hoon Bae, Dong Seog Eun, Woo Sung Lee, Jae Duk Lee, Jae Woo Lim, Hanmei Choi
  • Publication number: 20180033799
    Abstract: Disclosed are vertical memory devices and methods of manufacturing the same. The vertical memory device may include includes a substrate, a gate stack structure and channel structure on the substrate, and a charge trap structure between the gate stack structure and the channel structure. The gate stack structure includes conductive structures and insulation interlayer structures that are alternately stacked on each other in a vertical direction on the substrate such that cell regions and inter-cell regions are alternately arranged in the vertical direction. The channel structure penetrates through the gate stack structure in the vertical direction. The charge trap structure and the conductive structures define memory cells at the cell regions. The charge structure is configured to selectively store charges. The charge trap structure includes an anti-coupling structure in the inter-cell region for reducing a coupling between neighboring memory cells adjacent to each other in the vertical direction.
    Type: Application
    Filed: March 10, 2017
    Publication date: February 1, 2018
    Inventors: Kohji KANAMORI, Dong-Seog Eun
  • Publication number: 20180019257
    Abstract: A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of vertical holes extending in a direction perpendicular to the upper surface of the substrate to penetrate through the gate structure, and a plurality of vertical structures in the plurality of vertical holes, respectively, each vertical structure of the plurality of vertical structures including an embedded insulating layer, and a plurality of channel layers separated from each other, the plurality of channel layers being outside the embedded insulating layer.
    Type: Application
    Filed: April 7, 2017
    Publication date: January 18, 2018
    Inventors: Young Hwan SON, Won Chul JANG, Dong Seog EUN, Jae Hoon JANG
  • Publication number: 20170358597
    Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.
    Type: Application
    Filed: August 28, 2017
    Publication date: December 14, 2017
    Inventors: Byoung Il LEE, Kyung Jun SHIN, Dong Seog EUN, Ji Hye KIM, Hyun Kook LEE