Patents by Inventor Dong-Seog Eun

Dong-Seog Eun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170358590
    Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.
    Type: Application
    Filed: November 8, 2016
    Publication date: December 14, 2017
    Inventors: Shin-hwan KANG, Young-hwan SON, Dong-seog EUN, Chang-sup LEE, Jae-hoon JANG
  • Publication number: 20170294443
    Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
    Type: Application
    Filed: June 19, 2017
    Publication date: October 12, 2017
    Inventors: JONG WON KIM, SEUNG HYUN LIM, CHANG SEOK KANG, YOUNG WOO PARK, DAE HOON BAE, DONG SEOG EUN, WOO SUNG LEE, JAE DUK LEE, JAE WOO LIM, HANMEI CHOI
  • Patent number: 9773806
    Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: September 26, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung Il Lee, Kyung Jun Shin, Dong Seog Eun, Ji Hye Kim, Hyun Kook Lee
  • Patent number: 9716104
    Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: July 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Won Kim, Seung Hyun Lim, Chang Seok Kang, Young Woo Park, Dae Hoon Bae, Dong Seog Eun, Woo Sung Lee, Jae Duk Lee, Jae Woo Lim, HanMei Choi
  • Publication number: 20170170191
    Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.
    Type: Application
    Filed: August 31, 2016
    Publication date: June 15, 2017
    Inventors: BYOUNG IL LEE, JOONG SHIK SHIN, DONG SEOG EUN, KYUNG JUN SHIN, HYUN KOOK LEE
  • Patent number: 9640549
    Abstract: A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: May 2, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Won Lee, Joon-Hee Lee, Dong-Seog Eun, Chang-Hyun Lee
  • Publication number: 20170040337
    Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
    Type: Application
    Filed: January 5, 2016
    Publication date: February 9, 2017
    Inventors: Jong Won KIM, Seung Hyun LIM, Chang Seok KANG, Young Woo PARK, Dae Hoon BAE, Dong Seog EUN, Woo Sung LEE, Jae Duk LEE, Jae Woo LIM, HanMei CHOI
  • Publication number: 20160149010
    Abstract: According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.
    Type: Application
    Filed: February 2, 2016
    Publication date: May 26, 2016
    Inventors: Jin-Yeon WON, Joon-Hee LEE, Seung-Woo PAEK, Dong-Seog EUN
  • Patent number: 9281414
    Abstract: According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: March 8, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Yeon Won, Joon-Hee Lee, Seung-Woo Paek, Dong-Seog Eun
  • Publication number: 20150137216
    Abstract: A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend.
    Type: Application
    Filed: November 6, 2014
    Publication date: May 21, 2015
    Inventors: Seok-Won LEE, Joon-Hee LEE, Dong-Seog EUN, Chang-Hyun LEE
  • Publication number: 20140284695
    Abstract: According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.
    Type: Application
    Filed: January 9, 2014
    Publication date: September 25, 2014
    Inventors: Jin-Yeon WON, Joon-Hee LEE, Seung-Woo PAEK, Dong-Seog EUN
  • Patent number: 7736989
    Abstract: A method of forming a semiconductor device, where the method may include forming a first trench in a semiconductor substrate, forming first device isolation patterns that fill the first trench, forming spacers on sidewalls of the first device isolation patterns, forming a second trench in the semiconductor substrate between first device isolation patterns, and forming second device isolation patterns that fill the second trench. The second trench is formed using an etching process adopting the first device isolation pattern and the spacer as a mask.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: June 15, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Won Chang, Sung-Nam Chang, Seung-Gun Seo, Dong-Seog Eun
  • Patent number: 7700426
    Abstract: Provided is a nonvolatile memory device and a method of forming the nonvolatile memory device. The nonvolatile memory device includes a floating gate formed on a first active region doped with a first-conductivity-type dopant. The floating gate is doped with the first-conductivity-type dopant. Therefore, the thickness of a tunnel insulation layer can be kept thin, and the threshold voltage of a nonvolatile memory cell including the floating gate can be increased. As a result, the endurance of the tunnel insulation layer and the data retention characteristics of the nonvolatile memory cell is improved.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: April 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Kyung Kim, Sung-Nam Chang, Dong-Seog Eun
  • Patent number: 7541243
    Abstract: Methods of forming an integrated circuit device include forming first and second device isolation regions at side-by-side locations within a semiconductor substrate to thereby define a semiconductor active region therebetween. These first and second device isolation regions have sidewalls that extend vertically relative to the semiconductor active region. A first gate insulating layer is formed on a surface of the semiconductor active region. A central portion of the first gate insulating layer extending opposite the semiconductor active region is thinned to thereby define gate insulating residues extending adjacent sidewalls of the first and second device isolation regions. A second gate insulating layer is formed on the gate insulating residues to thereby yield a non-uniformly thick third gate insulating layer. A gate electrode is formed on the non-uniformly thick third gate insulating layer.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: June 2, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Seog Eun, Sung-Nam Chang
  • Publication number: 20090029520
    Abstract: A method of forming a semiconductor device, where the method may include forming a first trench in a semiconductor substrate, forming first device isolation patterns that fill the first trench, forming spacers on sidewalls of the first device isolation patterns, forming a second trench in the semiconductor substrate between first device isolation patterns, and forming second device isolation patterns that fill the second trench. The second trench is formed using an etching process adopting the first device isolation pattern and the spacer as a mask.
    Type: Application
    Filed: July 21, 2008
    Publication date: January 29, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-Won CHANG, Sung-Nam Chang, Seung-Gun Seo, Dong-Seog Eun
  • Publication number: 20080124866
    Abstract: Methods of forming an integrated circuit device include forming first and second device isolation regions at side-by-side locations within a semiconductor substrate to thereby define a semiconductor active region therebetween. These first and second device isolation regions have sidewalls that extend vertically relative to the semiconductor active region. A first gate insulating layer is formed on a surface of the semiconductor active region. A central portion of the first gate insulating layer extending opposite the semiconductor active region is thinned to thereby define gate insulating residues extending adjacent sidewalls of the first and second device isolation regions. A second gate insulating layer is formed on the gate insulating residues to thereby yield a non-uniformly thick third gate insulating layer. A gate electrode is formed on the non-uniformly thick third gate insulating layer.
    Type: Application
    Filed: February 2, 2007
    Publication date: May 29, 2008
    Inventors: Dong-Seog Eun, Sung-Nam Chang
  • Publication number: 20080093650
    Abstract: Provided is a nonvolatile memory device and a method of forming the nonvolatile memory device. The nonvolatile memory device includes a floating gate formed on a first active region doped with a first-conductivity-type dopant. The floating gate is doped with the first-conductivity-type dopant. Therefore, the thickness of a tunnel insulation layer can be kept thin, and the threshold voltage of a nonvolatile memory cell including the floating gate can be increased. As a result, the endurance of the tunnel insulation layer and the data retention characteristics of the nonvolatile memory cell is improved.
    Type: Application
    Filed: January 29, 2007
    Publication date: April 24, 2008
    Inventors: Tae-Kyung Kim, Sung-Nam Chang, Dong-Seog Eun
  • Patent number: 7348267
    Abstract: A method of fabricating a flash memory device produces a device that has a small cell area and yet a high coupling ratio. First, a basic structure is provided that includes a substrate, a field isolation film protruding from the substrate, and floating gates disposed on the substrate on opposite sides of the floating gate. A first etch process is performed to remove a portion of the field isolation film and thereby expose upper portions of the floating gates. Then, a second etch process is performed to knock off the edges of the floating gates. Thus, a large amount of space is secured between the floating gates for a dielectric film and a control gate.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: March 25, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Seog Eun, Sung-Hun Lee
  • Publication number: 20060154419
    Abstract: A method of fabricating a flash memory device produces a device that has a small cell area and yet a high coupling ratio. First, a basic structure is provided that includes a substrate, a field isolation film protruding from the substrate, and floating gates disposed on the substrate on opposite sides of the floating gate. A first etch process is performed to remove a portion of the field isolation film and thereby expose upper portions of the floating gates. Then, a second etch process is performed to knock off the edges of the floating gates. Thus, a large amount of space is secured between the floating gates for a dielectric film and a control gate.
    Type: Application
    Filed: January 9, 2006
    Publication date: July 13, 2006
    Inventors: Dong-Seog Eun, Sung-Hun Lee
  • Publication number: 20040241956
    Abstract: A trench isolation region can be formed in a device substrate by planarizing a first insulation layer in a trench of a substrate using chemical mechanical polishing so that the first insulation layer is removed from a surface of the substrate outside the trench and remains inside the trench, thereby forming an opening to a void beneath a surface of the first insulation layer. A further portion of the first insulation layer can be removed from inside the trench using a wet etch or a dry etch process to increase the opening to the void. A second insulation layer can be deposited in the void in the first insulation layer through the increased opening.
    Type: Application
    Filed: May 21, 2004
    Publication date: December 2, 2004
    Inventors: Dong-seog Eun, Kwang-shik Shin, Kyu-charn Park, Han-soo Kim