Patents by Inventor Dong-Seog Eun
Dong-Seog Eun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180033799Abstract: Disclosed are vertical memory devices and methods of manufacturing the same. The vertical memory device may include includes a substrate, a gate stack structure and channel structure on the substrate, and a charge trap structure between the gate stack structure and the channel structure. The gate stack structure includes conductive structures and insulation interlayer structures that are alternately stacked on each other in a vertical direction on the substrate such that cell regions and inter-cell regions are alternately arranged in the vertical direction. The channel structure penetrates through the gate stack structure in the vertical direction. The charge trap structure and the conductive structures define memory cells at the cell regions. The charge structure is configured to selectively store charges. The charge trap structure includes an anti-coupling structure in the inter-cell region for reducing a coupling between neighboring memory cells adjacent to each other in the vertical direction.Type: ApplicationFiled: March 10, 2017Publication date: February 1, 2018Inventors: Kohji KANAMORI, Dong-Seog Eun
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Publication number: 20180019257Abstract: A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of vertical holes extending in a direction perpendicular to the upper surface of the substrate to penetrate through the gate structure, and a plurality of vertical structures in the plurality of vertical holes, respectively, each vertical structure of the plurality of vertical structures including an embedded insulating layer, and a plurality of channel layers separated from each other, the plurality of channel layers being outside the embedded insulating layer.Type: ApplicationFiled: April 7, 2017Publication date: January 18, 2018Inventors: Young Hwan SON, Won Chul JANG, Dong Seog EUN, Jae Hoon JANG
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Publication number: 20170358590Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.Type: ApplicationFiled: November 8, 2016Publication date: December 14, 2017Inventors: Shin-hwan KANG, Young-hwan SON, Dong-seog EUN, Chang-sup LEE, Jae-hoon JANG
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Publication number: 20170358597Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.Type: ApplicationFiled: August 28, 2017Publication date: December 14, 2017Inventors: Byoung Il LEE, Kyung Jun SHIN, Dong Seog EUN, Ji Hye KIM, Hyun Kook LEE
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Publication number: 20170294443Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.Type: ApplicationFiled: June 19, 2017Publication date: October 12, 2017Inventors: JONG WON KIM, SEUNG HYUN LIM, CHANG SEOK KANG, YOUNG WOO PARK, DAE HOON BAE, DONG SEOG EUN, WOO SUNG LEE, JAE DUK LEE, JAE WOO LIM, HANMEI CHOI
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Patent number: 9773806Abstract: A semiconductor device includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating through the gate electrodes and the interlayer insulating layers, and a gate dielectric layer disposed on an external surface of the channel layer between the gate electrodes and the channel layer. In addition, the channel layer includes a first region extended in a direction perpendicular to a top surface of the substrate and a second region connected to the first region in a lower portion of the first region and including a plane inclined with respect to the top surface of the substrate.Type: GrantFiled: December 27, 2016Date of Patent: September 26, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung Il Lee, Kyung Jun Shin, Dong Seog Eun, Ji Hye Kim, Hyun Kook Lee
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Patent number: 9716104Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.Type: GrantFiled: January 5, 2016Date of Patent: July 25, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Won Kim, Seung Hyun Lim, Chang Seok Kang, Young Woo Park, Dae Hoon Bae, Dong Seog Eun, Woo Sung Lee, Jae Duk Lee, Jae Woo Lim, HanMei Choi
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Publication number: 20170170191Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.Type: ApplicationFiled: August 31, 2016Publication date: June 15, 2017Inventors: BYOUNG IL LEE, JOONG SHIK SHIN, DONG SEOG EUN, KYUNG JUN SHIN, HYUN KOOK LEE
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Patent number: 9640549Abstract: A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend.Type: GrantFiled: November 6, 2014Date of Patent: May 2, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok-Won Lee, Joon-Hee Lee, Dong-Seog Eun, Chang-Hyun Lee
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Publication number: 20170040337Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.Type: ApplicationFiled: January 5, 2016Publication date: February 9, 2017Inventors: Jong Won KIM, Seung Hyun LIM, Chang Seok KANG, Young Woo PARK, Dae Hoon BAE, Dong Seog EUN, Woo Sung LEE, Jae Duk LEE, Jae Woo LIM, HanMei CHOI
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Publication number: 20160149010Abstract: According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.Type: ApplicationFiled: February 2, 2016Publication date: May 26, 2016Inventors: Jin-Yeon WON, Joon-Hee LEE, Seung-Woo PAEK, Dong-Seog EUN
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Patent number: 9281414Abstract: According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.Type: GrantFiled: January 9, 2014Date of Patent: March 8, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Yeon Won, Joon-Hee Lee, Seung-Woo Paek, Dong-Seog Eun
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Publication number: 20150137216Abstract: A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend.Type: ApplicationFiled: November 6, 2014Publication date: May 21, 2015Inventors: Seok-Won LEE, Joon-Hee LEE, Dong-Seog EUN, Chang-Hyun LEE
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Publication number: 20140284695Abstract: According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.Type: ApplicationFiled: January 9, 2014Publication date: September 25, 2014Inventors: Jin-Yeon WON, Joon-Hee LEE, Seung-Woo PAEK, Dong-Seog EUN
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Patent number: 7736989Abstract: A method of forming a semiconductor device, where the method may include forming a first trench in a semiconductor substrate, forming first device isolation patterns that fill the first trench, forming spacers on sidewalls of the first device isolation patterns, forming a second trench in the semiconductor substrate between first device isolation patterns, and forming second device isolation patterns that fill the second trench. The second trench is formed using an etching process adopting the first device isolation pattern and the spacer as a mask.Type: GrantFiled: July 21, 2008Date of Patent: June 15, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Won Chang, Sung-Nam Chang, Seung-Gun Seo, Dong-Seog Eun
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Patent number: 7700426Abstract: Provided is a nonvolatile memory device and a method of forming the nonvolatile memory device. The nonvolatile memory device includes a floating gate formed on a first active region doped with a first-conductivity-type dopant. The floating gate is doped with the first-conductivity-type dopant. Therefore, the thickness of a tunnel insulation layer can be kept thin, and the threshold voltage of a nonvolatile memory cell including the floating gate can be increased. As a result, the endurance of the tunnel insulation layer and the data retention characteristics of the nonvolatile memory cell is improved.Type: GrantFiled: January 29, 2007Date of Patent: April 20, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Kyung Kim, Sung-Nam Chang, Dong-Seog Eun
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Patent number: 7541243Abstract: Methods of forming an integrated circuit device include forming first and second device isolation regions at side-by-side locations within a semiconductor substrate to thereby define a semiconductor active region therebetween. These first and second device isolation regions have sidewalls that extend vertically relative to the semiconductor active region. A first gate insulating layer is formed on a surface of the semiconductor active region. A central portion of the first gate insulating layer extending opposite the semiconductor active region is thinned to thereby define gate insulating residues extending adjacent sidewalls of the first and second device isolation regions. A second gate insulating layer is formed on the gate insulating residues to thereby yield a non-uniformly thick third gate insulating layer. A gate electrode is formed on the non-uniformly thick third gate insulating layer.Type: GrantFiled: February 2, 2007Date of Patent: June 2, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Seog Eun, Sung-Nam Chang
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Publication number: 20090029520Abstract: A method of forming a semiconductor device, where the method may include forming a first trench in a semiconductor substrate, forming first device isolation patterns that fill the first trench, forming spacers on sidewalls of the first device isolation patterns, forming a second trench in the semiconductor substrate between first device isolation patterns, and forming second device isolation patterns that fill the second trench. The second trench is formed using an etching process adopting the first device isolation pattern and the spacer as a mask.Type: ApplicationFiled: July 21, 2008Publication date: January 29, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-Won CHANG, Sung-Nam Chang, Seung-Gun Seo, Dong-Seog Eun
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Publication number: 20080124866Abstract: Methods of forming an integrated circuit device include forming first and second device isolation regions at side-by-side locations within a semiconductor substrate to thereby define a semiconductor active region therebetween. These first and second device isolation regions have sidewalls that extend vertically relative to the semiconductor active region. A first gate insulating layer is formed on a surface of the semiconductor active region. A central portion of the first gate insulating layer extending opposite the semiconductor active region is thinned to thereby define gate insulating residues extending adjacent sidewalls of the first and second device isolation regions. A second gate insulating layer is formed on the gate insulating residues to thereby yield a non-uniformly thick third gate insulating layer. A gate electrode is formed on the non-uniformly thick third gate insulating layer.Type: ApplicationFiled: February 2, 2007Publication date: May 29, 2008Inventors: Dong-Seog Eun, Sung-Nam Chang
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Publication number: 20080093650Abstract: Provided is a nonvolatile memory device and a method of forming the nonvolatile memory device. The nonvolatile memory device includes a floating gate formed on a first active region doped with a first-conductivity-type dopant. The floating gate is doped with the first-conductivity-type dopant. Therefore, the thickness of a tunnel insulation layer can be kept thin, and the threshold voltage of a nonvolatile memory cell including the floating gate can be increased. As a result, the endurance of the tunnel insulation layer and the data retention characteristics of the nonvolatile memory cell is improved.Type: ApplicationFiled: January 29, 2007Publication date: April 24, 2008Inventors: Tae-Kyung Kim, Sung-Nam Chang, Dong-Seog Eun