Patents by Inventor Dong-Seog Eun

Dong-Seog Eun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6737335
    Abstract: A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: May 18, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Dal Choi, Kyu-Charn Park, Dong-Seog Eun
  • Publication number: 20030197241
    Abstract: A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.
    Type: Application
    Filed: May 19, 2003
    Publication date: October 23, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-Dal Choi, Kyu-Charn Park, Dong-Seog Eun
  • Patent number: 6586804
    Abstract: A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: July 1, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Dal Choi, Kyu-Charn Park, Dong-Seog Eun
  • Publication number: 20020033516
    Abstract: A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.
    Type: Application
    Filed: September 7, 2001
    Publication date: March 21, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-Dal Choi, Kyu-Charn Park, Dong-Seog Eun