Abstract: A cloud streaming service system and a method and apparatus for providing a cloud streaming service are disclosed. The cloud streaming server previously generates a section clip for a section having high resource usage, and performs a shortcut streaming procedure for sending the previously generated clip, rather than a normal streaming procedure, during the corresponding section, thereby efficiently utilizing the resources of a cloud streaming service system and thus increasing the maximum number of simultaneously executable applications.

Abstract: The present invention discloses a matable and dematable electrical connecting structure characterized by comprising: a female coupling member having a first connecting portion; a male coupling member having a second connecting portion; and a connecting unit coupling the female coupling member and the male coupling member and electrically connecting the first and second connecting portions, wherein the connecting unit includes an inner conductive material which is electrically connected to the first connecting portion and is provided on the inner wall of an insert hole formed in the female connecting member, a column including a conductive material which is electrically connected to the second connecting portion, protruding from the male connecting member, and can be inserted in the insert hole, and one or more elastic pin including a surface of a conductive material which is extending in an outward direction from the column and elastically contacting the inner conductive material.

Abstract: The present invention relates to a carbon nanofibers growth method including (S1) depositing an alumina layer on a silicon substrate, (S2) depositing palladium on the alumina layer to form a palladium catalyst layer, and (S3) growing carbon nanofibers on the palladium catalyst layer by a chemical vapor deposition (CVD) method, and carbon nanofibers vertically grown on an alumina layer-deposited silicon substrate, the carbon nanofibers having tip ends with a radius of curvature less than or equal to 5 nm, a diameter less than or equal to 50 nm, a length more than or equal to 1 mm, and a length-diameter aspect ratio more than or equal to 50,000.

Abstract: Voltage generators may generate a level of a high target voltage with respect to a low external power supply voltage. A reference voltage generator includes a clamp regulator which is driven by a first power supply voltage supplied from an external source and receives a first voltage to generate a clamp voltage, and a level amplifier which is driven by a second power supply voltage that is higher than the first power supply voltage and receives the clamp voltage to generate a reference voltage. The clamp voltage may be set to have a voltage level which results in a successful restore operation with respect to a memory cell array in a dynamic random access memory (DRAM).

Abstract: Embodiments provide an apparatus controlling a low voltage DC-DC converter (LDC) in an electric vehicle that enables the LDC to autonomously wake up and operate when at least one of an ignition IGN signal and other electric components linked to the LDC is in the ON state and enables the LDC to recognize that other electric components linked to the LDC are all in the OFF state, and autonomously operate in a power-off state when other electric components linked to the LDC are all in the OFF state.

Abstract: A container unit and a display device including the same are disclosed. The container unit, containing a display unit, may include: a bottom chassis including i) a first portion spaced apart from a rear side of the display unit by a first distance, and ii) a second portion extending from the first portion and spaced apart from the rear side of the display unit by a second distance longer than the first distance, the second portion having a first opening. The display device may further include an insulation frame disposed between the second portion of the bottom chassis and the display panel, and having a second opening which is communicated with the first opening and smaller than the first opening, wherein one end of the insulation frame facing a central portion of the second opening has a chamfered structure at one side edge thereof.

Abstract: There are provided a control circuit for a digitally controlled oscillator and a control apparatus for a digitally controlled oscillator using the same. The control circuit for a digitally controlled oscillator includes: a peak detection circuit detecting amplitude of a signal output from the digitally controlled oscillator; and a transconductance control circuit comparing an output of the peak detection circuit with a predetermined reference signal to control a transconductance value of a negative transconductance circuit included in the digitally controlled oscillator.

Abstract: There are provided an analog-to-digital signal conversion method and apparatus therefor, and a digital phase locked loop circuit including the same. The analog-to-digital signal conversion method may include: generating a first digital output signal having N number of bits by comparing each of N number of delay signals detected from output terminals of N number of delay cells with a reference signal; generating a second digital output signal by comparing an auxiliary delay signal generated by an (N+1)th delay cell with the reference signal; and determining a change in a delay time of each of the N number of delay cells based on the first digital output signal and the second digital output signal.

Abstract: There are provided an analog-to-digital signal conversion method and apparatus therefor, and a digital phase locked loop circuit including the same. The analog-to-digital signal conversion method may include: generating a first digital output signal having N number of bits by comparing each of N number of delay signals detected from output terminals of N number of delay cells with a reference signal; generating a second digital output signal by comparing an auxiliary delay signal generated by an (N+1)th delay cell with the reference signal; and determining a change in a delay time of each of the N number of delay cells based on the first digital output signal and the second digital output signal.

Abstract: An arrangement in a network device for facilitating multiple connection speeds with a network is provided. The arrangement includes a set of network ports that includes a set of input network ports for receiving data traffic and a set of output network ports for outputting the data traffic from the network device. The arrangement also includes a logic component configured for managing the data traffic and for aggregating the data traffic. The arrangement further includes a monitoring port that is configured to receive the aggregated data traffic. The arrangement also includes a plurality of physical layer interfaces, wherein each physical layer interface is configured to support the multiple connection speeds. The arrangement moreover includes a media access controller that is configured to support at least a single connection speed of the multiple connection speeds.

Abstract: A spatial disturbance that occurs when an access is concentrated in a specific memory area in a volatile semiconductor memory like DRAM is properly solved by a memory controller. The memory controller includes a concentration access detection part generating a concentration access detection signal when an address for accessing a specific memory area among memory areas of volatile semiconductor memory is concentrically received. In the case that the concentration access detection signal is generated, the memory controller includes a controller for easing or preventing corruption of data which memory cells of the specific memory area and/or memory cells of memory areas adjacent to the specific memory area hold.

Abstract: Voltage generators may generate a level of a high target voltage with respect to a low external power supply voltage. A reference voltage generator includes a clamp regulator which is driven by a first power supply voltage supplied from an external source and receives a first voltage to generate a clamp voltage, and a level amplifier which is driven by a second power supply voltage that is higher than the first power supply voltage and receives the clamp voltage to generate a reference voltage. The clamp voltage may be set to have a voltage level which results in a successful restore operation with respect to a memory cell array in a dynamic random access memory (DRAM).

Abstract: An internal voltage generating circuit and a semiconductor memory device including the internal voltage generating circuit are disclosed. The internal voltage generating circuit includes a first voltage generating circuit, a second voltage generating circuit, and a third voltage generating circuit. The first voltage generating circuit stabilizes a first external supply voltage to generate a first internal voltage. The second voltage generating circuit stabilizes the first external supply voltage and a second external supply voltage to generate a second internal voltage having a voltage level higher than the first internal voltage. The third voltage generating circuit stabilizes the second internal voltage to generate a third internal voltage having a voltage level lower than the second internal voltage. Accordingly, the semiconductor memory device may be insensitive to a change in an external supply voltage and have small power consumption.

Abstract: A network arrangement for automatically displaying statistical data is provided. The arrangement includes a port for receiving data traffic, a physical interface layer for copying data traffic, and a bus for directing a copy of the data traffic to monitoring devices. The arrangement also includes logic arrangement for analyzing the copy of data traffic, which includes at least a Receive Data Valid signal (including a rising edge and a falling edge) and a Receive Clock signal (including a rising edge and a falling edge). The arrangement further includes incrementing a first counter when the Receive Data Valid rising edge is received and incrementing a second counter when at least one of the Receive Clock rising edge and the Receive Clock falling edge is received. The arrangement moreover includes logic arrangement for displaying statistical data pertaining to the data traffic and a visual display arrangement for displaying statistical data.

Abstract: A container unit and a display device including the same are disclosed. The container unit, containing a display unit, may include: a bottom chassis including i) a first portion spaced apart from a rear side of the display unit by a first distance, and ii) a second portion extending from the first portion and spaced apart from the rear side of the display unit by a second distance longer than the first distance, the second portion having a first opening. The display device may further include an insulation frame disposed between the second portion of the bottom chassis and the display panel, and having a second opening which is communicated with the first opening and smaller than the first opening, wherein one end of the insulation frame facing a central portion of the second opening has a chamfered structure at one side edge thereof.

Abstract: A network arrangement for automatically displaying statistical data is provided. The arrangement includes a port for receiving data traffic, a physical interface layer for copying data traffic, and a bus for directing a copy of the data traffic to monitoring devices. The arrangement also includes logic arrangement for analyzing the copy of data traffic, which includes at least a Receive Data Valid signal (including a rising edge and a falling edge) and a Receive Clock signal (including a rising edge and a falling edge). The arrangement further includes incrementing a first counter when the Receive Data Valid rising edge is received and incrementing a second counter when at least one of the Receive Clock rising edge and the Receive Clock falling edge is received. The arrangement moreover includes logic arrangement for displaying statistical data pertaining to the data traffic and a visual display arrangement for displaying statistical data.

Abstract: An arrangement in a network device for facilitating multiple connection speeds with a network is provided. The arrangement includes a set of network ports that includes a set of input network ports for receiving data traffic and a set of output network ports for outputting the data traffic from the network device. The arrangement also includes a logic component configured for managing the data traffic and for aggregating the data traffic. The arrangement further includes a monitoring port that is configured to receive the aggregated data traffic. The arrangement also includes a plurality of physical layer interfaces, wherein each physical layer interface is configured to support the multiple connection speeds. The arrangement moreover includes a media access controller that is configured to support at least a single connection speed of the multiple connection speeds.

Abstract: An arrangement in a network device for displaying statistical data pertaining to data traffic that traverses the network device is provided. The arrangement includes a power supply arrangement for providing power to circuitry of the network device. The arrangement also includes a set of network ports, which includes a set of input network ports for receiving the data traffic and a set of output network ports for outputting the data traffic from the network device. The arrangement further includes logic arrangement for analyzing data traffic and for displaying statistical data pertaining to the data traffic. The arrangement yet also includes a visual display arrangement, which is configured to display the statistical data, whereas the data traffic is configured to traverse the network device between the set of input network ports and the set of output network ports irrespective whether power is provided to the circuitry of the network device.

Abstract: An arrangement in a network device for facilitating at least one of multiple connection speeds with a network, active response between a monitoring device and an end-device, and power over Ethernet (POE) over a network is provided. As a facilitator of multiple connection speeds, the arrangement includes a plurality of physical layer interface (PHY) and media access controller (MAC) that are configured to support multiple speeds. As a facilitator of active response, the arrangement includes a logic arrangement for multicasting a set of instructions that is sent from a monitoring port. As a facilitator of POE, the arrangement is configured to receive data traffic (e.g., data packets and/or power packets) through a first network port and to send the data traffic out a second network port.

Abstract: I describe and claim a device and method for generating develop voltage signals. The device includes a sense amplifier to sense a voltage difference between a plurality of bit lines responsive to a develop voltage signal, and a voltage generator to generate the develop voltage signal responsive to a reference voltage signal and according to an electrical characteristic of at least one transistor associated with the sense amplifier.