Abstract: A method for forming a capacitor of a semiconductor device having a dielectric film of high dielectric constant having three-dimensional structure for securing capacitance of semiconductor device in order to have excellent deposition characteristics, by forming a storage electrode formed of Ru film on a semiconductor substrate and forming dielectric films formed of high dielectric constant materials having excellent step coverage on the surface of the storage electrode, the dielectric films having a stacked structure of a first dielectric film formed at low deposition speed and a second dielectric film formed at higher deposition speed by reducing the amount of added gas, thereby performing the subsequent process easily and improving yield and productivity of semiconductor device and then embodying high integration of semiconductor device.

Abstract: A method for forming a capacitor for a semiconductor device is provided. In the method, a storage electrode is formed of a polysilicon layer, and a hemispherical silicate glass (HSG) layer is optionally formed on the surface of the storage electrode to increase the surface area of the storage electrode. Next, a TaSiN layer as a diffusion barrier is formed, a TaON layer as a dielectric layer is formed, and then a TaSiN layer is formed on the TaON layer. Next, a plate electrode is formed on the TaSiN layer, thereby completing a capacitor. Diffusion of oxygen between the electrodes and the dielectric layer is effectively blocked, so that reduction of capacitance and occurrence of leakage current are prevented. Due to improved dielectric characteristics of the TaON layer, increasing the surface area of the dielectric layer—for example, by forming a HSG layer—may not be required, thereby increasing a processing margin between adjacent capacitors.

Abstract: A novel heat sink structure for being mounted to a module board to which semiconductor chips are attached and for dissipating or spreading heat generated from the semiconductor chips is disclosed. The heat sink comprises a heat sink base, and a coupling means for coupling the heat sink base to the module board. The coupling means passes through the heat sink base. The coupling means includes integrally formed upper and lower body portions, an orifice formed at least through the lower body portion, and a flanged base formed integral with the lower body portion. The flanged base fixes the coupling means to the heat sink base. The outer dimension of the upper body portion is smaller than the inner dimension of the lower body portion. As a result, many heat sinks can be stacked stably.

Abstract: The inventions herein feature an arrangement for controlling read and write operations in a semiconductor memory device, which can reduce power consumption by controlling data read and write operations in a DRAM having an open drain output buffer. The circuit for controlling the read and write operations in the semiconductor memory device includes a write unit for comparing potential states of bits of a write data according to a control signal, converting the write data into a first logic level and writing the converted data on DRAMs as an internal data with a flag bit having a first logic level, when a number of the bits having the first logic level is greater than a number of the bits having a second logic level, and writing the write data on the DRAMs as an internal data with a flag bit having the second logic level, when the number of the bits having the first logic level is equal to or smaller than the number of the bits having the second logic level.

Abstract: A novel heat sink structure for being mounted to a module board to which semiconductor chips are attached and for dissipating or spreading heat generated from the semiconductor chips is disclosed. The heat sink comprises a heat sink base, and a coupling means for coupling the heat sink base to the module board. The coupling means passes through the heat sink base. The coupling means includes integrally formed upper and lower body portions, an orifice formed at least through the lower body portion, and a flanged base formed integral with the lower body portion. The flanged base fixes the coupling means to the heat sink base. The outer dimension of the upper body portion is smaller than the inner dimension of the lower body portion. As a result, many heat sinks can be stacked stably.

Abstract: A duty cycle correction circuit of a delay locked loop circuit in a Rambus DRAM, decreasing a clock locking time by previously correcting a storage capacitor value to a setting value so as to provide a duty cycle correction within a short time in exiting a power save mode of delay locked loop, and accordingly, can realize a the power save mode capable of a high speed movement and without a time limit.

Abstract: A clock control circuit for a Rambus DRAM is provided which reduces power consumption by determining in advance whether an applied command is a read or current control command, and enabling a clock signal for externally outputting an internal data only during the read or current control command.

Abstract: A method for forming a capacitor for a semiconductor device is provided. In the method, a storage electrode is formed of a polysilicon layer, and a hemispherical silicate glass (HSG) layer is optionally formed on the surface of the storage electrode to increase the surface area of the storage electrode. Next, a TaSiN layer as a diffusion barrier is formed, a TaON layer as a dielectric layer is formed, and then a TaSiN layer is formed on the TaON layer. Next, a plate electrode is formed on the TaSiN layer, thereby completing a capacitor. Diffusion of oxygen between the electrodes and the dielectric layer is effectively blocked, so that reduction of capacitance and occurrence of leakage current are prevented. Due to improved dielectric characteristics of the TaON layer, increasing the surface area of the dielectric layer-for example, by forming a HSG layer-may not be required, thereby increasing a processing margin between adjacent capacitors.

Abstract: A method for manufacturing an inexpensive and safe titanium dioxide powder having an excellent photocatalytic ability and a high purity of anatase phase crystalline structure by utilizing meta-titanic acid as a starting material is disclosed. Meta-titanic acid is first neutralized by a basic solution, followed by adding a metal oxide. Then, the meta-titanic acid is spray dried using hot air to obtain spherical shape granules. The granules are then sintered to obtain the resulting titanium dioxide powder having small sized porous second particles and a high specific surface area. As a result, an economical and highly effective photocatalytic titanium dioxide powder can be obtained.

Abstract: This Rambus DRAM has a power save function which is not restricted in using time and has a short setting time, by forcibly compensating for a lost capacitor value in a memory cell to have a predetermined value, when a power save mode is changed to a normal mode.

Abstract: The inventions herein feature an arrangement for controlling read and write operations in a semiconductor memory device, which can reduce power consumption by controlling data read and write operations in a DRAM having an open drain output buffer. The circuit for controlling the read and write operations in the semiconductor memory device includes a write unit for comparing potential states of bits of a write data according to a control signal, converting the write data into a first logic level and writing the converted data on DRAMs as an internal data with a flag bit having a first logic level, when a number of the bits having the first logic level is greater than a number of the bits having a second logic level, and writing the write data on the DRAMs as an internal data with a flag bit having the second logic level, when the number of the bits having the first logic level is equal to or smaller than the number of the bits having the second logic level.

Abstract: In accordance with the present invention, there is provided a dual channel FIFO circuit to perform bidirectional data transfer under the control of a host computer between a host interface and a small computer system interface, comprising: a first multiplexing means for selecting one of the data from said host interface and the data from said small computer system interface; a single ported SRAM for storing the selected data by said first multiplexing means and outputting the data, which are indicated by pointers, according to the requests from said host interface or said small computer system interface; a second multiplexing means for selecting one of the data from said single ported SRAM and the data from said small computer system interface; a first staging memory means for storing the data to be outputted to said host interface; and a second staging memory means for storing the selected data by said second multiplexing means and transferring them to said second multiplexing means and said small computer s

Abstract: A circuit or plug/play (P/P) in a PCI bus which can store information in a PCI master/target device so that an address input board or component installed in a PCI local bus necessary for developing an information processing system adopting the PCI bus can support complete automatic, the circuit including controlling means for generating a plurality of latch enabling signals having a predetermined delay time, in accordance with a PCI reset signal, a clock signal and an address signal for reading data, input generating means having a plurality of input generating blocks and generating a plurality of data to be written in corresponding latches, in accordance with the PCI reset signal, data latching means having a plurality of latches, constituted by a plurality of latch groups corresponding to the plurality of input generating blocks, for writing data applied from the input generating means, in accordance with the latch enabling signals from the controlling means; and a PCI interface for reading and outputting c

Abstract: A front wheel suspension apparatus for a vehicle, includes an elastic tiebar member connected to a torsion bar and a strut bar, the elastic tiebar having an elastic material tube for absorbing any impact delivered from the strut bar, and outer or inner tube connected to a frame through a link for preventing the impact from being delivered to the frame.