Abstract: A fault analysis result generating system includes an extracting unit, a converting unit, a determining unit, and a result generating unit. The system extracts fault analysis files, converts the fault analysis files to a first predetermined file format which is easy to be processed, converts the fault analysis files with the first predetermined file format to a second predetermined file format, and then transfers the fault analysis files with the second predetermined file format to a learning sharing module.

Abstract: A water body self-generating electrolytic reduction module is applied to a water body containing oxidizing substances. The water body self-generating electrolytic reduction module includes a self-generating unit and an electrolysis unit. The self-generating unit is coupled to the electrolysis unit. When circulating in a water transmission pipeline, the water body drives the self-generating unit to generate an electric power and deliver the electric power to the electrolysis unit. Upon receiving the electric power, the electrolysis unit performs electrolysis on the water body circulating to the electrolysis unit, so that a reduction reaction occurs to the oxidizing substances in the water body.

Abstract: A fault analysis result generating system includes an extracting unit, a converting unit, a determining unit, and a result generating unit. The system extracts fault analysis files, converts the fault analysis files to a first predetermined file format which is easy to be processed, converts the fault analysis files with the first predetermined file format to a second predetermined file format, and then transfers the fault analysis files with the second predetermined file format to a learning sharing module.

Abstract: A fan delay controlling apparatus includes a connector connected to a fan of an electronic device, a power supplying module connected to the connector, and a power controlling module connected to the power supplying module. The power supplying module is connected to a fan power source and a stand-by power source. The power controlling module controls the power supplying module supply power to the fan when the electronic device including the fan powers off until an ambient temperature is lower than a predetermined value.

Abstract: An exemplary surge current alarm circuit includes a detecting circuit to detect a surge current and convert the surge current into a digital signal with a pulse width corresponding to a duration of an over value part of the surge current when the surge current is over a limitative current value; a processing circuit connected to the detecting circuit to receive the digital signal and generate an alarm signal when the pulse width of the digital signal is over a limitative time; and an alarm circuit connected to the processing circuit to give an alarm upon receiving the alarm signal from the processing circuit.

Abstract: A programmable logic device (PLD) data transfer cable includes a parallel interface, a programming interface, and a logic control circuit. The parallel interface is used for connecting to PLDs. The logic control circuit includes a first group of transmission channels, a second group of transmission channels, a first group of switches, and a second group of switches. The first and second group of switches control the working status of the first and second group of transmission channels respectively. The electrical connections between pins of the parallel interface and the programming interface when first group of transmission channels are activated are different with those when second group of transmission channels are activated.

Abstract: A circuit for indicating operating status of a plurality of hardware devices of a computer includes a detecting module, a decoding module, and an indicating module. The indicating module includes a dual color indicator and two electronic switches connected to a first input and a second input of the dual color indicator respectively. The detecting module detects an operating status of the plurality of hardware devices, and outputs state signals of each hardware device during power on self test of the computer. The decoding module decodes the state signals, and outputs level control signals to turn on or off the two electronic switches. The dual color indicator indicates operating status of the plurality of hardware devices by shifted to be at different indicating states by the two electronic switches correspondingly.

Abstract: Data locality optimization through object relocation may be implemented in a virtual machine including a just-in-time compiler. The just-in-time compiler generates load instruction maps for each compiled method. A profile collector is coupled to the just-in-time compiler to receive hardware profiling support. The profile collector takes samples of data cache misses. A garbage collector is coupled to the profile collector. The garbage collector deduces types of objects from the cache miss samples and adjusts garbage collection object copying heuristics to relocate objects for better cache locality based on those types.

Abstract: A switch-mode power supply for selectively providing power from a main power source and a standby power source to an electronic device is provided. The switch-mode power supply includes a signal input, a first transistor, a second transistor, a driving circuit, and a switching circuit. The signal input is used for receiving a control signal. The driving circuit and switching circuit connect the signal input to the gate of the second transistor in series. When the driving circuit detects the first transistor is switched off, the gate of the second transistor is immediately pulled up to open the second transistor, and when the driving circuit detects the first transistor is switched on, the gate of the second transistor is immediately pulled down to close the second transistor.

Abstract: A programmable logic device (PLD) data transfer cable includes a parallel interface, a programming interface, and a logic control circuit. The parallel interface is used for connecting to PLDs. The logic control circuit includes a first group of transmission channels, a second group of transmission channels, a first group of switches, and a second group of switches. The first and second group of switches control the working status of the first and second group of transmission channels respectively. The electrical connections between pins of the parallel interface and the programming interface when first group of transmission channels are activated are different with those when second group of transmission channels are activated.

Abstract: An exemplary motherboard tester includes a processor comprising a pair of data terminals for transmitting data; and an interface comprising: a pair of data terminals coupled to the data terminals of the processor respectively; at least one output terminal arranged for connecting to a corresponding pin of a chipset mounted on a motherboard to send a test signal generated by the processor to the pin; and at least one input terminal arranged for connecting to a test point on the motherboard which is electrically connected to the pin, to receive a feedback signal from the test point, wherein, the processor compares the feedback signal with the test signal to determine whether the pin of the chipset is normal, open, or shorted.

Abstract: An exemplary surge current alarm circuit includes a detecting circuit to detect a surge current and convert the surge current into a digital signal with a pulse width corresponding to a duration of an over value part of the surge current when the surge current is over a limitative current value; a processing circuit connected to the detecting circuit to receive the digital signal and generate an alarm signal when the pulse width of the digital signal is over a limitative time; and an alarm circuit connected to the processing circuit to give an alarm upon receiving the alarm signal from the processing circuit.

Abstract: An exemplary monitoring device includes: a time chip connected to a connector to generate a time signal and a count signal when the connector is working, the time signal indicating how long the connector is in use, the count signal indicating that the total number of times the connector has been used should be incremented by one; a processor connected to the time chip to receive the time signal and count signal, and generate a data signal including a total service time and a total number of times the connector has been used; a clock generator connected to the processor to provide a clock signal; and an output port connected to the processor to output the data signal. The monitoring device keeps a watch on a connector for showing the service information about the connector to make an operator know if the connector needs to be replaced.

Abstract: A drying apparatus includes a humidity sensor module, a micro control unit (MCU) module, an indicator circuit, and a fan module. The humidity sensor module measures relative humidity of air in a computer, and converts that measurement to an electronic signal. The MCU module receives the electronic signal from the humidity sensor module, and respectively outputs an indication signal and a control signal when the measured humidity is greater than a predetermined value stored in the MCU module. The indicator circuit indicates the humidity in the computer is too high when it receives the indication signal from the MCU module. The fan is activated when it receives the control signal from the MCU module.

Abstract: Data locality optimization through object relocation may be implemented in a virtual machine including a just-in-time compiler. The just-in-time compiler generates load instruction maps for each compiled method. A profile collector is coupled to the just-in-time compiler to receive hardware profiling support. The profile collector takes samples of data cache misses. A garbage collector is coupled to the profile collector. The garbage collector deduces types of objects from the cache miss samples and adjusts garbage collection object copying heuristics to relocate objects for better cache locality based on those types.

Abstract: Disclosed are a method, apparatus and system for dynamically managing layout of compiled code in a managed runtime environment. Profile feedback is generated during runtime, based on hardware event data that is gathered during runtime. A code manager dynamically relocates compiled code to reduce miss events based on the profile feedback. The code manager may also relocate virtual method tables in a virtual table region in order to reduce data miss events. The method does not require a prior run of an application program because profile feedback is based on event data that is tracked by hardware during execution of the software application and is not based on instrumented code.

Abstract: A switch-mode power supply for selectively providing power from a main power source and a standby power source to an electronic device is provided. The switch-mode power supply includes a signal input, a first transistor, a second transistor, a driving circuit, and a switching circuit. The signal input is used for receiving a control signal. The driving circuit and switching circuit connect the signal input to the gate of the second transistor in series. When the driving circuit detects the first transistor is switched off, the gate of the second transistor is immediately pulled up to open the second transistor, and when the driving circuit detects the first transistor is switched on, the gate of the second transistor is immediately pulled down to close the second transistor.

Abstract: A cable use tracking apparatus includes a switch module fixed to a cable, a detecting module, and a computer communicating with the detecting module. The switch module switches from a first state to a second state based on activity of the cable relative to an electronic device. The detecting module detects the switching of the states, and outputs result indicating signals. The computer counts and displays the number of times that the cable is used based on the indicating signals.

Abstract: An exemplary state monitoring circuit includes a data transform unit, a counter, and a clock generator. The data transform unit is connected to a system management bus (SMBUS) to obtain serial signals output from the SMBUS, and convert the serial signals to parallel signals. The counter is connected to a south bridge chip of the system and the data transform unit, for counting parallel signals converted by the data transform unit, if the count is finished, the counter sends a reset signal to the south bridge chip. The clock generator is connected to the counter for providing a clock frequency signal to the counter.

Abstract: An exemplary keyboard includes a first keyboard unit having a container defined in a side thereof, and a second keyboard unit pivotally attached to the first keyboard unit. The second keyboard includes a handle to drive the second keyboard unit to rotate between a first position in which the second keyboard unit is accommodated in the container of the first keyboard unit, and a second position in which the second keyboard unit is outside the first keyboard unit.