Patents by Inventor Dong-Hyun Im
Dong-Hyun Im has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973106Abstract: A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.Type: GrantFiled: July 5, 2022Date of Patent: April 30, 2024Assignee: SK hynix Inc.Inventors: Jae Hee Song, Dong Hyun Lee, Kyung Woong Park, Cheol Hwan Park, Ki Vin Im
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Patent number: 11942567Abstract: Provided is a method of manufacturing a light-emitting element, the method including positioning a substrate, forming a first separation layer, which includes a first sacrificial layer, an etching control layer on the first sacrificial layer, and a second sacrificial layer on the etching control layer, on the substrate, forming at least one first light-emitting element on the first separation layer, and separating the first light-emitting element from the substrate.Type: GrantFiled: July 15, 2021Date of Patent: March 26, 2024Assignee: Samsung Display Co., Ltd.Inventors: Jung Hong Min, Dae Hyun Kim, Hyun Min Cho, Jong Hyuk Kang, Dong Uk Kim, Seung A Lee, Hyun Deok Im, Hyung Rae Cha
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Publication number: 20240074708Abstract: It is disclosed a blood glucose prediction system and method using saliva-based artificial intelligence deep learning technique.Type: ApplicationFiled: September 1, 2023Publication date: March 7, 2024Applicant: DONG WOON ANATECH CO., LTD.Inventors: In Su Jang, Min Su Kwon, Hee Jung Kwon, Sung Hwan Chung, Eun Hye Im, Ji Won Kye, Eun Hyun Shim, Hee Jin Kim, Mi Rim Kim, Hyun Seok Cho, Dong Cheol Kim
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Patent number: 11715666Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.Type: GrantFiled: January 13, 2022Date of Patent: August 1, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Hyun Im, Kibum Lee, Daehyun Kim, Ju Hyung We, Sungmi Yoon
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Patent number: 11575019Abstract: Forming a semiconductor device includes forming a first conductive line on a substrate, forming a memory cell including a switching device and a data storage element on the first conductive line, and forming a second conductive line on the memory cell. Forming the switching device includes forming a first semiconductor layer, forming a first doped region by injecting a n-type impurity into the first semiconductor layer, forming a second semiconductor layer thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region, forming a second doped region by injecting a p-type impurity into an upper region of the second semiconductor layer, and forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region to form a P-N junction of the P-N diode in the second semiconductor layer.Type: GrantFiled: August 28, 2019Date of Patent: February 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho Kyun An, Dong Hyun Im
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Publication number: 20220165608Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.Type: ApplicationFiled: January 13, 2022Publication date: May 26, 2022Inventors: Dong-Hyun IM, Kibum LEE, Daehyun KIM, Ju Hyung WE, Sungmi YOON
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Publication number: 20220050739Abstract: Forming a semiconductor device includes forming a first conductive line on a substrate, forming a memory cell including a switching device and a data storage element on the first conductive line, and forming a second conductive line on the memory cell. Forming the switching device includes forming a first semiconductor layer, forming a first doped region by injecting a n-type impurity into the first semiconductor layer, forming a second semiconductor layer thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region, forming a second doped region by injecting a p-type impurity into an upper region of the second semiconductor layer, and forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region to form a P-N junction of the P-N diode in the second semiconductor layer.Type: ApplicationFiled: August 28, 2019Publication date: February 17, 2022Inventors: Ho Kyun AN, Dong Hyun IM
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Patent number: 11232973Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.Type: GrantFiled: December 27, 2019Date of Patent: January 25, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Hyun Im, Kibum Lee, Daehyun Kim, Ju Hyung We, Sungmi Yoon
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Patent number: 10998619Abstract: A ring type antenna module and a jig for manufacture for manufacturing the same, which can communicate regardless of the orientation when mounted on a ring type wearable device and can easily process the size are provided. The ring type antenna module includes a base substrate having flexibility on which a radiation pattern is formed, a terminal part formed on one end of the base substrate and connected to one end of the radiation pattern, and the other terminal part formed on the other end of the base substrate and connected to the other end of the radiation pattern; and the size of the ring type antenna module is adjusted by varying the coupled location between the terminal part and the other terminal part.Type: GrantFiled: June 9, 2017Date of Patent: May 4, 2021Assignee: AMOTECH CO., LTD.Inventors: Beon-Jin Kim, Chi-Ho Lee, Dong-Hyun Im
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Publication number: 20200402839Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.Type: ApplicationFiled: December 27, 2019Publication date: December 24, 2020Inventors: Dong-Hyun IM, Kibum LEE, Daehyun KIM, Ju Hyung WE, Sungmi YOON
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Patent number: 10868016Abstract: A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.Type: GrantFiled: July 1, 2019Date of Patent: December 15, 2020Assignee: SAMSUNG ELECTRONICS., LTD.Inventors: Dong-Hyun Im, Daehyun Kim, Hoon Park, Jae-Hong Seo, Chunhyung Chung, Jae-Joong Choi
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Patent number: 10833088Abstract: A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.Type: GrantFiled: February 28, 2020Date of Patent: November 10, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Hyun Im, Daehyun Kim, Hoon Park, Jae-Hong Seo, Chunhyung Chung, Jae-Joong Choi
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Patent number: 10748909Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.Type: GrantFiled: December 12, 2019Date of Patent: August 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jinwon Ma, Jun-Noh Lee, Dong-Hyun Im, Youngseok Kim, Kongsoo Lee
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Publication number: 20200203352Abstract: A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.Type: ApplicationFiled: February 28, 2020Publication date: June 25, 2020Inventors: DONG-HYUN IM, DAEHYUN KIM, HOON PARK, JAE-HONG SEO, CHUNHYUNG CHUNG, JAE-JOONG CHOI
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Publication number: 20200119021Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.Type: ApplicationFiled: December 12, 2019Publication date: April 16, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jinwon MA, Jun-Noh Lee, Dong-Hyun IM, Youngseok Kim, Kongsoo Lee
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Patent number: 10535663Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.Type: GrantFiled: January 11, 2019Date of Patent: January 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jinwon Ma, Jun-Noh Lee, Dong-Hyun Im, Youngseok Kim, Kongsoo Lee
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Publication number: 20190393225Abstract: A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.Type: ApplicationFiled: July 1, 2019Publication date: December 26, 2019Inventors: DONG-HYUN IM, DAEHYUN KIM, HOON PARK, JAE-HONG SEO, CHUNHYUNG CHUNG, JAE-JOONG CHOI
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Publication number: 20190384669Abstract: Forming a semiconductor device includes forming a first conductive line on a substrate, forming a memory cell including a switching device and a data storage element on the first conductive line, and forming a second conductive line on the memory cell. Forming the switching device includes forming a first semiconductor layer, forming a first doped region by injecting a n-type impurity into the first semiconductor layer, forming a second semiconductor layer thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region, forming a second doped region by injecting a p-type impurity into an upper region of the second semiconductor layer, and forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region to form a P-N junction of the P-N diode in the second semiconductor layer.Type: ApplicationFiled: August 28, 2019Publication date: December 19, 2019Inventors: Ho Kyun AN, Dong Hyun IM
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Patent number: 10403735Abstract: Forming a semiconductor device includes forming a first conductive line on a substrate, forming a memory cell including a switching device and a data storage element on the first conductive line, and forming a second conductive line on the memory cell. Forming the switching device includes forming a first semiconductor layer, forming a first doped region by injecting a n-type impurity into the first semiconductor layer, forming a second semiconductor layer thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region, forming a second doped region by injecting a p-type impurity into an upper region of the second semiconductor layer, and forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region to form a P-N junction of the P-N diode in the second semiconductor layer.Type: GrantFiled: January 19, 2017Date of Patent: September 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Ho Kyun An, Dong Hyun Im
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Patent number: 10373959Abstract: A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.Type: GrantFiled: July 31, 2018Date of Patent: August 6, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Hyun Im, Daehyun Kim, Hoon Park, Jae-Hong Seo, Chunhyung Chung, Jae-Joong Choi