Abstract: A substrate supporting plate that may prevent deposition on a rear surface of a substrate and may easily unload the substrate. The substrate supporting plate may include a substrate mounting portion and a peripheral portion surrounding the substrate mounting portion. An edge portion of a top surface of the substrate mounting portion may be anodized. A central portion of the top surface of the substrate mounting portion may not be anodized.

Abstract: A computing device includes at least one memory, and at least one processor configured to generate, based on first analysis on a pathological slide image, first biomarker expression information, generate, based on a user input for updating at least some of results of the first analysis, second biomarker expression information about the pathological slide image, and control a display device to output a report including medical information about at least some regions included in the pathological slide image, based on at least one of the first biomarker expression information or the second biomarker expression information.

Abstract: A light emitting element may include a first semiconductor layer, an emission layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the emission layer, an insulating film, and an electrode layer. The insulating film may enclose a side surface of the first semiconductor layer, a side surface of the emission layer, and a side surface of the second semiconductor layer. The electrode layer may be disposed on the second semiconductor layer and the insulating film. The insulating film may not enclose the electrode layer.

Abstract: Implementations disclosed describe wireless devices and methods for mitigating aggressive medium reservations. A first wireless device comprises a transceiver and a processor coupled to the transceiver. The processor is to detect, within a first transmission received by the transceiver from a second wireless device via a first wireless communication channel, a pattern of medium reservations comprising a reservation duration that satisfies a threshold duration value. The processor is further to cause, in response to detecting the pattern of medium reservations, the transceiver to send a second transmission to an access point (AP) wireless device. The second transmission includes an indication of the pattern of medium reservations. The processor is further to detect a medium reservation mitigation signal within a third transmission received by the transceiver from the AP wireless device.

Abstract: An example electronic device includes a housing; a touchscreen display; a microphone; at least one speaker; a button disposed on a portion of the housing or set to be displayed on the touchscreen display; a wireless communication circuit; a processor; and a memory. When a user interface is not displayed on the touchscreen display, the electronic device enables a user to receive a user input through the button, receives user speech through the microphone, and then provides data on the user speech to an external server. An instruction for performing a task is received from the server. When the user interface is displayed on the touchscreen display, the electronic device enables the user to receive the user input through the button, receives user speech through the microphone, and then provides data on the user speech to the external server.

Abstract: A computing apparatus includes: at least one memory; and at least one processor, wherein the processor generates quantitative information regarding at least one cell included in a region of interest of a pathological slide image by analyzing the pathological slide image, generates qualitative information regarding at least one tissue included in the pathological slide image by analyzing the pathological slide image, and controls a display apparatus to output at least one of the quantitative information and the qualitative information on the pathological slide image according to a manipulation of a user.

Abstract: An apparatus of tilting a seat cushion of a vehicle, includes a tilting motor, a pinion gear, a sector gear, and a tilting link which perform the tilting operation of the seat cushion and exert a binding force in a tilted state of the seat cushion and are provided to be connected to both of one side and the other side of a seat cushion frame, and has two sector gears positioned on left and right sides and connected to each other by a connection bar so that, by strengthening a binding force of the front portion of the seat cushion, it is possible to secure the safety of passengers in the event of a collision.

Abstract: A battery module includes: a battery cell assembly having a plurality of battery cells; a top plate configured to cover an upper side of the battery cell assembly; a bottom plate configured to cover a lower side of the battery cell assembly; a sensing assembly disposed to cover a front side and a rear side of the battery cell assembly; a pair of side plates disposed at side surfaces, respectively, of the battery cell assembly; and a pair of compression pads disposed between the pair of side plates and the battery cell assembly, respectively.

Abstract: The present invention relates to a method of manufacturing polycrystalline silicon ingot using a crucible in which an oxygen exhaust passage is formed by single crystal or polycrystalline rods, the method including the steps of: manufacturing the single crystal or polycrystalline silicon rods each having the shape of a quadrilateral pillar; putting the single crystal or polycrystalline quadrilateral pillar-shaped silicon rods into the crucible in such a manner as to be arranged close to one another along the inner peripheral surface of the crucible to thus form a space portion inside the single crystal or polycrystalline silicon rods, into which silicon chunks are put, and the oxygen exhaust passages between the inner peripheral surface of the crucible and the respective surfaces of the single crystal or polycrystalline silicon rods oriented toward the inner peripheral surface of the crucible; putting the silicon chunks into the space portion of the crucible; and melting and crystallizing the silicon chunks.

Abstract: A memory device and an operating method of the memory device are provided. The operating method comprises receiving an activation-refresh command from a memory controller, decoding a target address and an internal command from the activation-refresh command, and performing an activation operation based on the internal command for the target address and performing a refresh operation on at least one block to which the target address does not belong.

Abstract: A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.

Abstract: A substrate supporting plate that may prevent deposition on a rear surface of a substrate and may easily unload the substrate. The substrate supporting plate may include a substrate mounting portion and a peripheral portion surrounding the substrate mounting portion. An edge portion of a top surface of the substrate mounting portion may be anodized. A central portion of the top surface of the substrate mounting portion may not be anodized.

Abstract: A substrate supporting plate that may prevent deposition on a rear surface of a substrate and may easily unload the substrate. The substrate supporting plate may include a substrate mounting portion and a peripheral portion surrounding the substrate mounting portion. An edge portion of a top surface of the substrate mounting portion may be anodized. A central portion of the top surface of the substrate mounting portion may not be anodized.

Abstract: A memory system includes a logic circuit and a phase locked loop (PLL) circuit. The logic circuit determines a first frequency of a first clock using a first signal and generates a second signal for adjusting the first frequency of the first clock. The PLL circuit receives a second clock, and generates the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal. When a second frequency of the second clock varies, the logic circuit determines the first frequency of the first clock such that the first frequency of the first clock generated by the PLL circuit is uniform, and operates based on the first clock having the first frequency adjusted by the second signal.

Abstract: A memory device includes an output pin, a mode register, a signal generator configured to generate a detection clock output signal including one of a random data pattern and a hold data pattern in response to first and second control signals from the mode register, and output the detection clock output signal through the output pin. The random data pattern includes pseudo-random data generated by the memory device. The hold data pattern is a fixed pattern pre stored in the memory device. The detection clock output signal is used for a clock and data recovery operation.

Abstract: A memory device performs first training including a plurality of loop operations to align a main clock signal and a data clock signal, which are received from a memory controller. A method of operating the memory device includes generating division ratio information indicating a division ratio set based on a frequency ratio of the main clock signal to the data clock signal and transmitting the division ratio information to the memory controller to perform the first training.

Abstract: A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.

Abstract: A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.

Abstract: A magnetic random access memory (MRAM), and a memory module, memory system including the same, and method for controlling the same are disclosed. The MRAM includes magnetic memory cells configured to change between at least two states according to a magnetization direction, and a mode register supporting a plurality of operational modes.

Abstract: A memory system includes a logic circuit and a phase locked loop (PLL) circuit. The logic circuit determines a first frequency of a first clock using a first signal and generates a second signal for adjusting the first frequency of the first clock. The PLL circuit receives a second clock, and generates the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal. When a second frequency of the second clock varies, the logic circuit determines the first frequency of the first clock such that the first frequency of the first clock generated by the PLL circuit is uniform, and operates based on the first clock having the first frequency adjusted by the second signal.