Abstract: A pixel may include: a first transistor including a second electrode, a first electrode electrically connected to a first power line, and a gate electrode connected to a first node; a second transistor including a second electrode, a first electrode electrically connected to a data line, and a gate electrode electrically connected to a first scan line; a third transistor connected between the first node and the data line, and including a gate electrode electrically connected to a second scan line; a first capacitor including a first electrode connected to the second electrode of the second transistor, and a second electrode connected to the first node; a second capacitor connected between the first power line and the first node; and a light emitting element between a second power line and the first transistor, and including a second electrode electrically connected to the second power line.

Abstract: Present invention relates to a semiconductor device including a buried gate structure. A semiconductor device comprises a substrate; a first fluorine-containing layer over the substrate; a trench formed in the first fluorine-containing layer and extended into the substrate; a gate dielectric layer formed over the trench; a gate electrode formed over the gate dielectric layer and filling a portion of the trench; a second fluorine-containing layer formed over the gate electrode; and a fluorine-containing passivation layer between the gate dielectric layer and the gate electrode.

Abstract: A pixel may include: a first transistor including a second electrode, a first electrode electrically connected to a first power line, and a gate electrode connected to a first node; a second transistor including a second electrode, a first electrode electrically connected to a data line, and a gate electrode electrically connected to a first scan line; a third transistor connected between the first node and the data line, and including a gate electrode electrically connected to a second scan line; a first capacitor including a first electrode connected to the second electrode of the second transistor, and a second electrode connected to the first node; a second capacitor connected between the first power line and the first node; and a light emitting element between a second power line and the first transistor, and including a second electrode electrically connected to the second power line.

Abstract: This application relates to a robot arm structure and a manipulator of a surgical robot including the robot arm structure. The robot arm structure includes a first robot arm unit and a second robot arm unit. The first robot arm unit includes a plurality of first link arms, a first joint unit mounted on one of the first link arms and rotating the one of the first link arms about a first axis and a second joint unit installed on at least one of the plurality of first link arms to adjust a length of the at least one link arm. The second robot arm unit includes a second link arm connected to one of the first link arms and a third joint unit using a lengthwise direction of the second link arm as a first rotary shaft and rotating the second link arm.

Abstract: According to embodiments of the disclosure, a pixel includes a driving transistor including a gate electrode, a first electrode electrically connected to a first power line and a second electrode electrically connected to a light emitting element, a body of a semiconductive layer constituting the driving transistor being electrically connected to the first power line.

Abstract: A display device includes signal lines and pixels connected thereto. A first pixel includes a first transistor including a first gate electrode, a first channel region overlapping the first gate electrode, a first source region, and a second drain region facing the first source region, with the first channel region interposed between the first source region and the second drain region. A third transistor includes a third gate electrode, a third channel region overlapping the third gate electrode, a third drain region connected to the first gate electrode, and a third source region facing the third drain region with the third channel region interposed between the third source region and the third drain region. A shielding part overlaps a boundary between the third source region and the third channel region and does not overlap a boundary between the third drain region and the third channel region.

Abstract: A semiconductor device includes: a substrate including a trench; a bottom gate electrode suitable for gap-filling a lower portion of the trench and including a silicon-doped first metal nitride; and a top gate electrode formed over the bottom gate electrode, and including a silicon-doped second metal nitride having a higher silicon content than a silicon content of the bottom gate electrode and having a higher ratio of a metal content to a nitrogen content than a ratio of a metal content to a nitrogen content of the bottom gate electrode.

Abstract: Disclosed is a waste gas treatment apparatus for semiconductor and display processes, the apparatus including: a pre-treatment unit having an inlet and an outlet formed therein, and configured to spray a cleaning solution to waste gas introduced through the inlet to primarily treat in the waste gas; a reaction unit configured to simultaneously treat fluorine compounds and nitrous oxide (N2O) in waste gas discharged from the pre-treatment unit; a post-treatment unit configured to spray a cleaning solution to waste gas discharged from the reaction unit to secondarily treat in the waste gas; and a heat exchange unit installed between the pre-treatment unit and the reaction unit.

Abstract: A display device includes signal lines and pixels connected thereto. A first pixel includes a first transistor including a first gate electrode, a first channel region overlapping the first gate electrode, a first source region, and a second drain region facing the first source region, with the first channel region interposed between the first source region and the second drain region. A third transistor includes a third gate electrode, a third channel region overlapping the third gate electrode, a third drain region connected to the first gate electrode, and a third source region facing the third drain region with the third channel region interposed between the third source region and the third drain region. A shielding part overlaps a boundary between the third source region and the third channel region and does not overlap a boundary between the third drain region and the third channel region.

Abstract: The present specification relates to a plasma and VHP combined sterilizer comprising a housing. More particularly, the plasma and VHP combined sterilizer comprises: a discharge unit, which is provided at the upper end of a housing and discharges predetermined amount of vaporized hydrogen peroxide; a suction fan, which is provided at one side of the housing and suctions the outer air and discharged hydrogen peroxide; a plasma generation unit including a plurality of plasma modules for generating the outer air and hydrogen peroxide, which are suctioned through the suction fan, as plasma ions through plasma discharge; and a control unit for controlling the overall operation of the plasma and VHP combined sterilizer.

Abstract: A semiconductor device includes: a gate trench formed into a semiconductor substrate; a gate dielectric layer formed in the gate trench to cover an inside surface of the gate trench; and a gate electrode disposed over the gate dielectric layer to fill the gate trench, wherein the gate electrode includes: second crystal grains formed in the gate trench; and first crystal grains disposed between the second crystal grains and the gate dielectric layer and having a smaller crystal grain size than the second crystal grains.

Abstract: Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the method for fabricating semiconductor device may include forming a trench in a substrate; forming a gate dielectric layer over the trench, embedding a first dipole inducing portion in the gate dielectric layer on a lower side of the trench, filling a lower gate over the first dipole inducing portion, embedding a second dipole inducing portion in the gate dielectric layer on an upper side of the trench and forming an upper gate over the lower gate.

Abstract: A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate, which partially fills the trench, over the gate dielectric layer, forming a low work function layer over the lower gate, forming a spacer over the low work function layer, etching the low work function layer to be self-aligned with the spacer in order to form vertical gate on both upper edges of the lower gate, and forming an upper gate over the lower gate between inner sidewalls of the vertical gate.

Abstract: Embodiments of the present invention provides a semiconductor device with improved electrical characteristics and a method of fabricating the same. A semiconductor device according to an embodiment of the present invention comprises: a substrate including a trench; a gate dielectric layer formed along a sidewall surface and a bottom surface of the trench; a lower gate electrode filling a lower portion of the trench over the gate dielectric layer and formed of a first metal nitride, the first metal nitride having a first grain size; an upper gate electrode partially filling the trench over the lower gate electrode, including a low work function control element, and formed of a second metal nitride, the second metal nitride having a second grain size bigger than the first grain size; and a capping layer gap-filling the remainder of the trench over the upper gate electrode.

Abstract: A display device includes signal lines and pixels connected thereto. A first pixel includes a first transistor including a first gate electrode, a first channel region overlapping the first gate electrode, a first source region, and a second drain region facing the first source region, with the first channel region interposed between the first source region and the second drain region. A third transistor includes a third gate electrode, a third channel region overlapping the third gate electrode, a third drain region connected to the first gate electrode, and a third source region facing the third drain region with the third channel region interposed between the third source region and the third drain region. A shielding part overlaps a boundary between the third source region and the third channel region and does not overlap a boundary between the third drain region and the third channel region.

Abstract: Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the method may include forming a trench in a substrate, lining a surface of the trench with an initial gate dielectric layer, forming a gate electrode to partially fill the lined trench, forming a sacrificial material spaced apart from a top surface of the gate electrode and to selectively cover a top corner of the lined trench, removing a part of the initial gate dielectric layer of the lined trench which is exposed by the sacrificial material in order to form an air gap, and forming a capping layer to cap a side surface of the air gap, over the gate electrode.

Abstract: An embodiment of the present invention provides a semiconductor device capable of improving gate induced drain leakage and a method for fabricating the same, According to an embodiment of the present invention, a semiconductor device comprises a substrate including a trench; a gate insulating layer covering a bottom surface and a sidewall of the trench; and a gate electrode structure and a capping layer sequentially stacked on the gate insulating layer and filling the trench, wherein the gate electrode structure includes: a first gate electrode including a metal nitride; a second gate electrode formed over the first gate electrode, having the same metal nitride as the first gate electrode, and having a lower work function than that of the first gate electrode; and a third gate electrode formed over the second gate electrode, having a thickness smaller than that of the second gate electrode, and including a non-metal material.

Abstract: A semiconductor device includes: a substrate including a gate trench; a gate dielectric layer formed along sidewalls and bottom surfaces of the gate trench; a high work function layer and a lower gate electrode that fill a bottom portion of the gate trench over the gate dielectric layer; an upper gate electrode including a low work function adjusting element over the lower gate electrode and including the same metal nitride as a material of the lower gate electrode; and a capping layer that gap-fills the other portion of the gate trench over the upper gate electrode.

Abstract: A semiconductor device includes: a trench formed in a substrate; a gate dielectric layer covering sidewalls and a bottom surface of the trench; a first gate electrode gap-filling a bottom portion of the trench over the gate dielectric layer; a second gate electrode including a metal nitride which is the same as the first gate electrode over the first gate electrode and doped with a low work function adjusting element; a buffer layer covering a top surface of the second gate electrode and the gate dielectric layer exposed over second gate electrode; and a capping layer gap-filling the other portion of the trench over the buffer layer.

Abstract: A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a lower gate, which partially fills the trench, over the gate dielectric layer, forming a low work function layer over the lower gate, forming a spacer over the low work function layer, etching the low work function layer to be self-aligned with the spacer in order to form vertical gate on both upper edges of the lower gate, and forming an upper gate over the lower gate between inner sidewalls of the vertical gate.