Abstract: The disclosure relates to an electronic device and a method for wireless communication including a power amplification circuit. According to an embodiment, an electronic device may include: a radio frequency processing module comprising radio frequency circuitry, a first power amplification circuit connected to the radio frequency processing module, a second power amplification circuit connected to the radio frequency processing module and the first power amplification circuit, and a front-end module comprising circuitry connected to the second power amplification circuit and an antenna and configured to transmit a signal, wherein the second power amplification circuit is configured to acquire, from the first power amplification circuit, a first signal obtained by amplifying a signal output from the radio frequency processing module and a second signal by amplifying a signal output from the radio frequency processing module.

Abstract: A semiconductor package includes a first substrate, a first semiconductor chip and a passive device which are laterally spaced apart from each other on the first substrate and are disposed face-up on the first substrate, a first molding part surrounding the first semiconductor chip and the passive device on the first substrate, a second semiconductor chip disposed on the first molding part and electrically connected to the first semiconductor chip and the passive device, a second molding part surrounding the second semiconductor chip on the first molding part, first through-electrodes vertically penetrating the first molding part, at least some of first through-electrodes electrically connect the first substrate to the second semiconductor chip, and external terminals provided under the first substrate.

Abstract: A semiconductor package includes a frame structure having a core portion and a lower pad under the core portion. A cavity penetrates the core portion, and a semiconductor chip is arranged in the cavity and has an active surface on which a bump pad is arranged and a non-active surface facing the active surface. A redistribution structure is positioned under the frame structure and the semiconductor chip, and is connected to the lower pad and the bump pad. A molding member covers the frame structure and the semiconductor chip and fills the cavity. The molding member surrounds a lower surface of the frame structure, the active surface of the semiconductor chip, the lower pad, and the bump pad.

Abstract: A Butler matrix circuit includes: a phase shifter that shifts the phase of a signal, the width of the phase shifter and/or the density of a dielectric material in the phase shifter being set so that the characteristic impedance of the lowest-order mode in the phase shifter varies in accordance with a predetermined function; and a coupler that divides a signal or crosses signals, the density of a dielectric material in a coupled portion between a first waveguide and a second waveguide arranged in parallel being varied in the coupler.

Abstract: In a waveguide, density of a dielectric material in the waveguide is set so that a characteristic impedance of a lowest-order mode in the waveguide varies in accordance with a predetermined function.

Abstract: In a waveguide, a width of the waveguide is set so that a characteristic impedance of a lowest-order mode in the waveguide varies in accordance with a predetermined function.

Abstract: A transmission device includes: a multiplex circular array antenna including a plurality of circular array antennas in which a plurality of antenna elements are arranged in a circle; a plurality of Butler circuits connected to the multiplex circular array antenna; and one or more Butler circuits connected to one or more linear array antennas including some antenna elements among the plurality of antenna elements of the multiplex circular array antenna.

Abstract: A reception device includes a first antenna, a second antenna, and a control unit that combines signals of a radio wave in a first orbital angular momentum (OAM) mode and a radio wave in a second OAM mode having a sign only that is different from a sign of the first OAM mode, received by the first antenna, with signals obtained by rotating OAM phases of the radio wave in the first OAM mode and the radio wave in the second OAM mode received by the second antenna by a predetermined angle to extract a signal of the radio wave in the first OAM mode, and combines signals of the radio wave in the first OAM mode and the radio wave in the second OAM mode received by the second antenna with signals obtained by rotating OAM phases of the radio wave in the first OAM mode and the radio wave in the second OAM mode received by the first antenna by the predetermined angle to extract a signal of the radio wave in the second OAM mode.

Abstract: An OAM multiplexing communication system uses one or more OAM modes and multiplexes signals of one or more sequences for each OAM mode. A transmitting station includes a transmitting antenna using an M-UCA, and an OAM mode generation unit that simultaneously generates one or more OAM modes from each UCA. A receiving station includes a receiving antenna equivalent to the M-UCA, an OAM mode separation unit that separates signals received by each UCA for each OAM mode, and a received signal processing unit that estimates channel information for each OAM mode and performs an equalization process for each OAM mode by using a receiving weight calculated from the channel information. The received signal processing unit is configured to estimate, for each OAM mode, channel information of another OAM mode causing interference and calculate the receiving weight of a subject OAM mode by using the channel information of the subject OAM mode and said another OAM mode.

Abstract: A method of manufacturing a fan-out semiconductor package includes forming a frame having a through-hole and including one or more wiring layers; forming a semiconductor chip in the through-hole of the frame; forming an encapsulant covering an upper surface of each of the frame and the semiconductor chip, and filling a space between a wall surface of the through-hole of the frame and a side surface of the semiconductor chip; forming a connection structure below each of the frame and the semiconductor chip; forming a first metal pattern layer on an upper surface of the encapsulant; forming an insulating material on the upper surface of the encapsulant and covering the first metal pattern layer; and forming a second metal pattern layer on the insulating material, a first metal via passing through the insulating material, and a second metal via passing through the insulating material and the encapsulant.

Abstract: A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.

Abstract: A method of manufacturing a semiconductor package may include forming a first substrate including a redistribution layer, providing a second substrate including a semiconductor chip and an interconnection layer on the first substrate to connect the semiconductor chip to the redistribution layer, forming a first encapsulation layer covering the second substrate, and forming a via structure penetrating the first encapsulation layer. The forming the via structure may include forming a first via hole in the first encapsulation layer, forming a photosensitive material layer in the first via hole, exposing and developing the photosensitive material layer in the first via hole to form a second encapsulation layer having a second via hole, and filling the second via hole with a conductive material. A surface roughness of a sidewall of the first encapsulation layer may be greater than a surface roughness of a sidewall of the second encapsulation layer.

Abstract: The present invention provides a catalyst structure having a core-shell structure comprising a core comprising a metal and a shell formed on the core, wherein the shell comprises a metal hydroxide crystal or a metal oxide crystal formed uniformly in shape and size perpendicular to the surface of the metal, wherein the metal hydroxide crystal or the metal oxide crystal have a 2D structure or a 1D structure, and preparation method thereof.

Abstract: A semiconductor package includes: a first redistribution layer including a first wiring; a die located on the first redistribution layer; and a shielding structure surrounding the die from an upper surface and side surfaces of the die, wherein the shielding structure includes: a shielding wall that is spaced apart from the side surfaces of the die and surrounds the side surfaces of the die; and a shielding cover that is spaced apart from the upper surface of the die and surrounds the upper surface of the die.

Abstract: A semiconductor package including a redistribution substrate with a first insulating layer, one or more second insulating layers on the first insulating layer, and a plurality of redistribution layers. The first insulating layer includes a first photosensitive resin having an elongation of 60% or more and toughness of 70 mJ/mm3 or more. The one or more second insulating layers include a second photosensitive resin having an elongation in a range of 10% to 40% and toughness of 40 mJ/mm3.

Abstract: A semiconductor device includes a substrate having a recess region, a first electrode in the recess region and having a three-dimensional network structure, a first dielectric layer in the recess region and covering the first electrode, a second electrode in the recess region and covering the first dielectric layer, and a molding layer filling a remaining portion of the recess region and covering the second electrode.

Abstract: A switch in an electronic device includes a substrate, a first signal line, a second signal line, and a ground bridge. The first signal line is on the substrate and extends in a first direction. The second signal line is on the substrate and is spaced apart from the first signal line in a first direction parallel with the first signal line to branch the wireless communication signal at a first point and a second point of the first signal line. The ground bridge is at least partially movable in a space between the first signal line and the second signal line. A first capacitor is between a first point of the first signal line and one end of the second signal line, and a second capacitor is between a second point of the first signal line and the other end of the second signal line.

Abstract: A semiconductor package includes a frame having a first surface and a second surface, and including a wiring structure and a through-hole. The package further includes a first redistribution structure disposed on the first surface of the frame and including a first insulating layer and a first redistribution layer on the first insulating layer and connected to the wiring structure, a bridge die in the through-hole and having an interconnector, and an encapsulant surrounding the bridge die, and covering the second surface of the frame. The package further includes a second redistribution structure disposed on the encapsulant, and including a second insulating layer and a second redistribution layer on the second insulating layer and connected to the interconnector and the wiring structure, and a plurality of semiconductor chips disposed on the second redistribution structure, connected to the second redistribution layer, and electrically connected to each other through the interconnector.

Abstract: A semiconductor package includes a redistribution portion including an insulating layer, a redistribution layer, and a redistribution via, an under-bump metallurgy (UBM) layer below the redistribution portion and including a UBM pad on a lower surface of the redistribution portion and a UBM via on the UBM pad to penetrate through the insulating layer, a semiconductor chip on an upper surface of the redistribution portion and electrically connected to the redistribution layer, an adhesive layer between the UBM layer and the insulating layer and including a conductive material, and a connection bump below the UBM pad and connected to the UBM layer. The UBM pad has a first diameter, and the UBM via has a second diameter, less than the first diameter, and an upper surface of the UBM pad is located on the same level as, or a level lower than, a lower surface of the insulating layer.

Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.