Abstract: A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An interrupt request identification code is assigned to each interrupt request and stored in the nesting buffer. The interrupt request identification codes used to reference the interrupt requests are stored in order of their priority. Each nesting buffer need have only a number of entries equal to the number of priority levels.

Abstract: A data bus for connecting information processing devices is configurable into a plurality of subbusses in order to fully utilize the data bus capacity. The size and data transfer direction of each subbus, as well as the data transfer speed of each subbus, is independent of the other subbusses. Also, the data bus can be reconfigured to meet changing system requirements. A data bus controller is thus provided to accomplish this data bus reconfiguration. The reconfiguration may be accomplished in accordance with one of a plurality of information flow templates which may be stored in a memory. A method of configuring a data bus is also provided wherein information transfer needs of a system are identified and the data bus is configured according to the identified information transfer means. The reconfiguration in accordance with the information transfer needs may be accomplished in accordance with one or more information flow templates which may be stored in a memory.

Abstract: An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further provided for comparing the priority level of the interrupt lines, latching the lower priority requests in a stand-by mode, and directing servicing of the highest priority level. An in-service register is provided for storing the identification of any request line that is being serviced by the microprocessor. In one embodiment, a set of signal lines are coupled between the in-service register and external terminals of the integrated circuit on which the interrupt controller is fabricated. A power management unit may be coupled to the external pins of the integrated circuit and thereby receives real-time information regarding an interrupt request that is currently being serviced and regarding interrupt service routines that have completed.

Abstract: A system for effecting communications between a computing device and a plurality of peripheral devices which comprises a bus controller for controlling the communications, a plurality of feedback generator circuits for providing operational status information, each of the plurality of peripheral devices having an associated one of the plurality of feedback generator circuits. The system further comprises a bus for conveying signals between the bus controller and the plurality of peripheral devices. In the preferred embodiment, each of the plurality of peripheral devices has a respective address and each of the plurality of feedback generator circuits contains the operational status information for its respective peripheral device.

Abstract: A multiprocessing computer system which includes an interrupt controller coupled to an expansion bus. The programmable interrupt controller has multiple storage locations at the same address for multiple CPUs. The CPUs are coupled to a host bus which in turn is coupled to the expansion bus by means of a bus bridge. An arbiter is coupled to the host bus for arbitrating bus mastership amongst the CPUs. CPU host owner identification for access to the storage locations is transferred across bus bridge to the programmable interrupt controller synchronized with the buffered address and data.

Abstract: A non-volatile memory chip enable encoding method allows the storage of both boot code and user application software within a common memory array. The chip enable encoding method further allows a variable number of memory banks to be provided within the non-volatile memory array and allows the system to power-up and execute the boot code before the array configurations are selected by firmware. In one embodiment, a memory controller includes four chip enable output lines for selectively enabling a plurality of ROM banks. One of the ROM banks includes boot code that is executed by the system microprocessor during system boot. If the user requires a ROM array consisting of four ROM banks, a separate chip enable output line is connected to each ROM bank. If the user instead requires a ROM array consisting of, for example, eight ROM banks, an external decoder may be connected to the four chip enable output lines.

Abstract: An interrupt controller includes an interrupt request register for receiving interrupt requests from various peripherals or I/O devices via a set of request lines. A priority resolver is further provided for comparing the priority level of the interrupt lines, latching the lower priority requests in a stand-by mode, and directing servicing of the highest priority level. An in-service register is provided for storing the identification of any request line that is being serviced by the microprocessor. In one embodiment, a set of signal lines are coupled between the in-service register and external terminals of the integrated circuit on which the interrupt controller is fabricated. A power management unit may be coupled to the external pins of the integrated circuit and thereby receives real-time information regarding an interrupt request that is currently being serviced and regarding interrupt service routines that have completed.

Abstract: A method and apparatus for transferring original data which includes images, between two stations located a distance apart, without actual transmission of the image portion of the data. A library of images are provided at each of the stations. The image to be transferred is processed into a description of the image which allows the reproduction of the image at the receiving end of the transmission using the images contained in the image library in the receiving station.

Abstract: A method of allocating bandwidth among a plurality of devices communicatively connected through a data bus provides for determining a data need of at least one of the plurality of devices, allocating portions of the data bus to the devices in response to the data need, and transmitting data between the devices on the allocated portions of the data bus. The portions of the data bus can be subbusses, each comprising at least one bit line. The data need can be based on a measure of fullness of a buffer corresponding to the at least one device. The data need can be provided as feedback from the buffer to a data bus controller which allocates the portions of the data bus. The method can use rules for assigning the subbusses which are stored in a memory. A processor can change the rules to accommodate changing conditions in the data bus.

Abstract: A symmetrical multiprocessing system is provided that includes a central interrupt control unit. The central interrupt control unit is coupled to a plurality of processing units and to a plurality of interrupt sources. The interrupt sources include a plurality of peripheral devices coupled to a first peripheral bus, such as a PCI bus. The interrupt sources also include devices coupled to a second peripheral bus, such as an ISA bus. The central interrupt control unit is operative in two modes. In a first mode, referred to as a pass through mode, interrupts from ISA peripheral devices are provided through an interrupt controller, such as cascaded type 8259 interrupt controllers, to the central interrupt control unit. The central interrupt control unit then passes the interrupt directly to a master processing unit. PCI interrupts are provided through a PCI mapper to other available interrupt inputs of the interrupt controller.

Abstract: A dockable computer system includes a portable computer (notebook or laptop) and a docking station (base unit). The portable computer and docking station both include a communication system so that messages can be communicated when the docking station is in an undocked state preparatory to a docked state. The communication system is preferably an infrared communication system. A communication protocol is also provided for generating an advance notice signal to warn of an impending dock. The communication protocol includes a CONNECT message, a CONNECT DETECTED message, and a CONFIRM message. Preferably, the CONNECT message is sent at a non-standard AT/PC baud rate. The communication system allows the dockable computer system to advantageously generate an advance notice signal of an impending dock and to transfer parameters necessary for the employment of sophisticated protective measures which protect the active buses of the portable computer and docking station during a docking event.

Abstract: An integrated processor is provided that includes a CPU core, a local bus coupled to the CPU core, and a variety of peripheral such as a memory controller, a direct memory access controller, and an interrupt controller coupled to the local bus. A bus interface unit is further provided to interface between the CPU local bus and a PCI standard multiplexed peripheral bus. The CPU core, the memory controller, the direct memory access controller, the interrupt controller, and the bus interface unit are all incorporated on a common integrated circuit chip. A local bus control unit is further provided that is capable of generating a loading signal and an address strobe signal synchronously with certain bus cycles that are executed on the PCI bus. The local bus control unit allows external peripheral devices that are compatible with the CPU local bus protocols to be connected through the PCI bus.

Abstract: An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, interrupt controller, and timer for monitoring the internal interrupt and bus request signals of the integrated processor. The power management message unit may also monitor other selected activities of the integrated processor depending upon the system requirements. Based on the detected activities, if any, the power management message unit encodes a message on a power management message bus to thereby provide information regarding the internal events of the integrated processor to an outside power management unit. The power management message bus is channeled from the integrated processor at a set of package pins that are isolated from the standard external peripheral bus of the integrated processor.

Abstract: A computer system includes a bus arbiter for providing immediate access to a bus in response to an external requirement or event. In a dockable computer system capable of hot docking or warm docking, the bus arbiter grants exclusive, non-preemptive access to the buses to the docking agent which is capable of quieting (rendering inactive) the bus of the portable computer and docking station in response to a notice signal. The notice signal is indicative of a change of states from the undocked state to the docked state or from the docked state to the undocked state. The notice signal may be provided from software, a user-actuated switch, or an infrared signal. In an audio-capable computer, the bus arbiter provides exclusive non-preemptive access to the digital signal processing peripheral device so that audio glitches are avoided.

Abstract: A non-volatile memory controller is provided which is connectable directly to the local bus of a computer system and which allows access to one or more 32-bit banks of ROM and to an 8-bit bank of non-volatile memory. The 8-bit bank of non-volatile memory may be used, for example, to store BIOS code, and may be implemented using a ROM or flash memory device. The non-volatile memory controller includes a data router, a sequencer, and a set of output latches for routing the 8-bit BIOS code (stored within the 8-bit bank) to selected byte lanes of the local bus and for converting the 8-bit data to 32-bit local bus data. The non-volatile memory controller further supports high performance, 32-bit accesses to the user software stored within the 32-bit banks. If the system designer or user instead must maximize the memory capacity of the computer system, the 8-bit bank of memory may be replaced with a larger 32-bit bank of memory.

Abstract: A dockable computer system is capable of performing symmetrical multi-processing operations. More particularly, the dockable computer system includes a portable computer and a host station (docking station), each including a resident CPU. The dockable computer system is capable of operating in a docked state in which the portable computer is physically joined with the host station and an undocked state in which the portable computer is physically separate from the host station. In the docked state, the dockable computer system is capable of performing demanding computational tasks such as video conferencing as one of the CPUs in either the portable computer or host station is dedicated to the video conferencing operation. The dockable computer system preferably includes a communication channel for transmitting multi-processing support signals between the portable computer and the host station.

Abstract: A computer system is provided that includes an interrupt driven system management mode during which system management code is accessed. In one embodiment, a lock-out register is provided to prevent accesses to the system management code while the computer system is operating in its normal mode. In one embodiment, an interrupt control unit is coupled to the ICE interrupt line of the microprocessor core, and controls a memory control unit in accordance with assertions of an external "debug" interrupt signal and an external SMM (system management mode) interrupt signal. If the debug interrupt signal is asserted while the microprocessor core is operating in its normal mode, the interrupt control unit responsively asserts the ICE interrupt signal to the microprocessor core, thereby, causing the microprocessor core to execute ICE code.

Abstract: A data communication system includes an express bus, a plurality of local buses, and a plurality of local/express bridges, each local/express bridge connecting a corresponding local bus to the express bus. A plurality of local/local bridges each connect two corresponding local buses. The plurality of local buses and the plurality of local/local bridges comprise a local path.

Abstract: A dockable computer system is capable of performing hot docking or warm docking. Hot docking refers to an ability to dock when the portable computer or docking station are running at full power. Warm docking refers to an ability to dock when the portable computer and docking station are running in a reduced power state. The dockable computer system employs a docking agent which is capable of quieting (rendering inactive) the buses of the portable computer and docking station in response to a notice signal. The notice signal is indicative of a change of states from the undocked state to the docked state or from the docked state to the undocked state. The notice signal can be provided from software, a user-actuated switch, or an infrared signal. The docking agent preferably quiets the system bus by idling the system bus or asserting bus ownership or bus mastership over the system bus. The docking agent is able to assert bus ownership or bus mastership over the system bus.

Abstract: In a dockable computer system capable of hot docking or warm docking, a docking safe circuit drives the bus of the portable computer and docking station to a docking safe state in response to a DOCK signal. The DOCK signal may be a notice signal indicative of a change of state from the undocked state to the docked state or from the docked state to the undocked state. The notice signal may be provided from software, a user-actuated switch or an infrared signal. Preferably, the docking safe state or dockable state is a state in which: the ground conductors of the buses are referenced to a common ground potential; the buses are "quiet" or non-transitioning; the bidirectional terminals on the bus of the portable computer are set to an output state; the bidirectional terminals of the bus of the docking station are set to an input state; and the signaling levels of the buses have the same voltage potential. Preferably, the present invention is implemented on a peripheral component interconnect (PCI) bus.