Abstract: A direct memory access controller is provided that performs DMA transfers by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The DMA configuration address range is the range of address values to which the configuration registers of the DMA controller are mapped for receiving initialization data. Accordingly, other peripheral devices that may be connected to the local bus will not respond to the I/O access cycle. An address disable signal is further not required to disable the address decoders of other I/O peripheral devices not involved in the DMA transfer.

Abstract: A direct memory access controller implements a two-cycle approach for performing a desired DMA transfer by executing both a memory access cycle and an I/O access cycle. During the memory access cycle, the address location of system memory to be accessed is driven on the addressing lines of a local bus. During the I/O access cycle, an address value within a DMA configuration address range is driven on the address lines of the local bus. The lower two order bits of the address value are encoded to provide byte lane information to a peripheral device during the I.backslash.O access cycle. The peripheral device responsively receives or provides data at the specified byte lane. As a result, peripheral devices that may be connected to the local bus will not respond to the I/O access cycle, while encoded byte lane information is provided to the desired peripheral device without requiring dedicated byte select lines.

Abstract: An integrated processor that employs a bus interface unit to accommodate high performance data transfers via an external peripheral interconnect bus with multiplexed address/data lines. The peripheral interconnect bus, which may be a PCI standard bus, accommodates data transfers between an internal bus of the integrated processor and PCI peripheral devices. The integrated processor further includes a sub-bus control unit that generates a set of side-band control signals that allow the external derivation of a lower performance secondary bus, such as an ISA bus, without requiring a complete set of external pins for the secondary bus on the integrated processor. The derivation of the secondary bus is accomplished with an external data buffer and an external address latch which are controlled by the side-band control signals. Separate address and data lines from the integrated processor for the secondary bus are not required.

Abstract: An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, interrupt controller, and timer for monitoring the internal interrupt and bus request signals of the integrated processor. The power management message unit may also monitor other selected activities of the integrated processor such as activities of a floating-point coprocessing subunit. Based on the detected activities, if any, the power management message unit encodes a message on a power management message bus to thereby provide information regarding the internal events of the integrated processor to an external power management unit. Power management decisions are made by an external power management unit.

Abstract: An apparatus for managing system interrupt operations in a computing system including a processing unit and peripheral devices. The apparatus comprises a transmission circuit for transmitting signals which effects operative connection among the peripheral devices and the processing unit; an interrupt drive circuit for generating interrupt signals associated with each peripheral device drives the transmission circuit from a first signal level to a second signal level to effect generating an interrupt signal; and an acknowledge drive circuit for generating an acknowledge signal by the processing unit. Each acknowledge drive circuit drives the transmission circuit from an initial signal level to an indicating signal level to effect generation of an acknowledge signal, and drives the transmission circuit from the indicating signal level to the initial signal level upon termination of the acknowledge signal.

Abstract: An apparatus for managing communication within a computing system which includes a processing unit and a plurality of peripheral units. The processing unit receives information from a plurality of loci within the computing system and determines an enablement profile in response to such information according to predetermined criteria. The processing unit responds to the enablement profile to selectively enable specified peripheral units. The apparatus comprises a monitoring circuit for monitoring the enablement profile; a logic circuit for logically treating the enablement profile and generating a feedback signal representative of the enablement profile; and a transmission circuit for communicating the feedback signal from the logic circuit to the processing unit. The processing unit responds to the feedback signal to determine whether to employ a transfer trapping discipline whereby transfers destined for a non-enabled peripheral unit are stored until the non-enabled unit is enabled.

Abstract: An integrated digital processing apparatus for use in a computing device. The apparatus comprises a central processor for effecting processing functions according to a program, a plurality of bus-accommodating devices for accommodating direct operative connection of peripheral devices via a plurality of buses, a single internal bus for accommodating communications internal of the apparatus among the central processing unit and the plurality of bus-accommodating devices, and an internal bus control for controlling utilization of the internal bus. The apparatus is, preferably, configured as an integrated digital circuit on a single substrate.

Abstract: A system for controlling communications among a computer processing unit and a plurality of peripheral devices which are arrayed in operative connection with a plurality of external buses. The system comprises a bus control circuit for effecting operative routing of address information regarding a respective peripheral device from the computer processing unit to an appropriate external bus, the respective peripheral device being in operative connection with the appropriate external bus. The bus control circuit also effects operative routing of data information from the respective peripheral device to another of the plurality of peripheral devices or to the computer processing unit according to the address information. The system further comprises a plurality of buffers for establishing operative interfaces between the system and each of the plurality of external buses and an internal bus for facilitating communications among the plurality of buffers, the bus control circuit, and the computer processing unit.

Abstract: An apparatus for use with a host computing system for controlling access to a first data bus which is external of the host computing system and which first data bus is operatively connected with a second data bus internal of the host computing system. The apparatus comprises a local processing unit which is configured substantially the same as the host processing unit and is driven by a separate local program distinct from the host processing program driving the host processing unit. The apparatus further comprises a supplemental processing circuit for processing information, which supplemental processing circuit is responsive to the host processing unit and to the local processing unit to determine whether the host processing unit or the local processing unit has operative access to the first data bus. In its preferred embodiment, the first data bus and the second data bus are operatively connected by a configurable buffer circuit for effecting data bus connection.

Abstract: An apparatus for use with a computing device for controlling communications with a plurality of peripheral devices, each of which peripheral devices is operatively connected with a bus and is identified by an address. The apparatus comprises a control circuit for transmitting address information to the bus to effect interrogation of the plurality of peripheral devices, respective of the pluraity of peripheral devices being responding, or ready, peripheral devices according to address information transmitted by the control circuit. A plurality of modal circuits are provided for establishing a plurality of operational modes for the apparatus, as well as a decision circuit for effecting designation of selected of the plurality of modal circuits.

Abstract: The invention is an apparatus for use with a computing device for generating a substitute acknowledgement to a first input signal when the computing device is in an operational hiatus. The apparatus comprises a logical processing circuit for indicating presence of the first input signal depending upon the state of a second input signal, and a logical circuit for producing an output signal which is representative of a selection of one of the plurality of logical inputs. The selection of logical inputs is determined by the state of the second input signal. The first input signal is a hold request signal and comprises a first logical input to the logical processing circuit. A second logical input is a hold acknowledgement signal which is generated by the computing device in response to the presence of the first input signal when the computing device is not in an operational hiatus.