Abstract: A compilier methodology including a stand alone memory interface which provides a user specified memory device of a required number of words of memory of a required bits per word. The stand alone memory interface is a tool to provide a menu showing multiple ways in which the user's request can be physically configured by varying the number of rows of memory, the number of blocks of memory, and the column multiplexing factor of the memory array. From this menu the user selects the memory configuration that best meets the user's requirements and is provided with either various models or representations (views) of the selected memory configuration or a GDS format data file. The views can be used to design large scale integrated circuits in which the memory device is embedded while the data file is used to generate photo mask for making the memory device as an integrated circuit.

Abstract: A method and apparatus for continuously drying and regenerating ceramic beads for use in process gas moisture drying operations such as glove boxes. A microwave energy source is coupled to a process chamber to internally heat the ceramic beads and vaporize moisture contained therein. In a preferred embodiment, the moisture laden ceramic beads are conveyed toward the microwave source by a screw mechanism. The regenerated beads flow down outside of the screw mechanism and are available to absorb additional moisture.

Abstract: The present invention is an improved method and related apparatus for quantitatively analyzing machine working fluids and other aqueous compositions such as wastewater which contain various mixtures of cationic, neutral, and/or anionic surfactants, soluble soaps, and the like. The method utilizes a single-phase, non-aqueous, reactive titration composition containing water insoluble bismuth nitrate dissolved in glycerol for the titration reactant. The chemical reaction of the bismuth ion and glycerol with the surfactant in the test solutions results in formation of micelles, changes in micelle size, and the formation of insoluble bismuth soaps. These soaps are quantified by physical and chemical changes in the aqueous test solution. Both classical potentiometric analysis and turbidity measurements have been used as sensing techniques to determine the quantity of surfactant present in test solutions.

Abstract: A configurable decode circuit (11) having a plurality of inputs (12), a clock input (13), an output (14), and an output (16) is described. The configurable decode circuit (11) is a nor type decoder configurable to different address widths. A latch (17) stores the decode results. A bias circuit (29) enables the configurable decode circuit (11) starting a decode cycle. A differential input stage is coupled between the latch (17) and bias circuit (29). One side of the differential input stage comprises a plurality of transistors (23) coupled in parallel. Each control electrode of the plurality of transistors (23) is coupled to a respective input of inputs (12). The other side of the differential input stage comprises a transistor (28) coupled between the latch (17) and the bias circuit (29). A control electrode of the transistor (28) is coupled to common first electrodes of the plurality of transistors (23).

Abstract: A memory circuit uses sense amplifiers to amplify a low level differential data signal from the memory cells to full logic levels. A first sense amplifier converts the low level differential data signal to an intermediate differential voltage level at first and second nodes during the read cycle. A second sense amplifier converts the intermediate differential voltage level to the full logic level. The first and second sense amplifiers are powered down after sensing is complete. A circuit drives the intermediate differential data signal to an equilibrium voltage level when the sensing is complete to reduce the power up delay time of the second sense amplifier and thereby increase the operating speed of the memory circuit. A latching circuit is synchronized with the power down of the first sense amplifier to latch the output logic level at the end of the read cycle.

Abstract: A write priority detector in a multiport memory prioritizes write operations to memory cell by activating one of its enable signals to a memory cell upon receiving multiple address signals at different write ports of the multiport memory, each attempting to access the same memory cell. The other enable signals are de-activated. One prioritization scheme provides first-come first-serve access to the memory cell among completing address signals. Alternately, a fixed priority scheme always gives one enable signal first priority.

Abstract: A memory sense amplifier with a latch circuit is provided. The combination of a sense amplifier and a latch circuit allows for increased speed operation and minimum space requirements on an integrated circuit. The memory sense amplifier receives complementary input logic signals that are typically from a memory cell and provides latched complementary output logic signals in response to the voltage levels of the complementary input logic signals.

Abstract: The present invention provides a voltage reference level using a bipolar output transistor to provide a reference voltage on a reference output line. A control circuit is used for varying the current to the base of the output transistor in response to the load on the reference output line. In addition, the control circuit provides the reference level to the output transistor. The MOS control circuit and the bipolar output transistor are fabricated on the same chip using a BICMOS process. The voltage reference provided by the control circuit is derived from a voltage level provided by a resistor coupled between the positive voltage supply and a current source.

Abstract: The present invention provides an ECL EPROM circuit which uses a MOS memory cell. The invention includes a technique for programming the memory cell using MOS voltage levels, and also includes circuitry for reading the memory cell at ECL voltage levels. Thus, the programming and reading paths are split to give the ease of programming and the reprogrammability of MOS EPROM devices combined with the reading speed of PROM devices using ECL voltage levels. In one embodiment, two parallel paths are provided to a memory cell to enable it to separately receive reading and writing (programming) signals. The reading path employs ECL components for reading the cell, while the writing path contains MOS components for programming and verifying the cell. The memory cell itself contains a MOS memory element, an ECL pass element, and a sense element coupling the MOS memory element to the ECL pass element.

Abstract: A power transition circuit protects a bipolar-CMOS (BiCMOS) circuit during power transitions. Reference signals proportional to the voltage supplied to the protected circuit are monitored, and the power transition circuit determines from the voltage differential between the reference signals whether a power transition is occurring. If a transition is present, the transition circuit disables the protected BiCMOS circuit for as long as the power transition exists. An independent input signal allows the power transition circuit to disable the protected BiCMOS circuit in response to other conditions.

Abstract: A BiCMOS write-recovery method and circuit for recovering bit lines in a digital memory system provides approximately 1 nS recovery time and allows a 256K BiCMOS SRAM to achieve 10 nS access time. All bit lines in the memory system connected to a column not being read are held at a high potential, approximately equal to the upper power supply. During a write, one bit line is pulled low and its complementary bit line is clamped with a bipolar transistor to an intermediate potential, thereby preloading the complementary bit line. Following a write, the bit line that was pulled low is pulled up with a bipolar transistor to the intermediate voltage. Simultaneously, the bit line and the complementary bit line are shunted together, then returned to the high potential. Undesired bootstrap capacitance effects in the bipolar transistors are minimized by connecting a plurality of pull-up transistors in parallel, and by feeding the clamping transistors with low impedance drivers.

Abstract: A biCMOS interface circuit receives a plurality of incoming signals at a first level and supplies a plurality of output signals at a second level. The interface circuit establishes control voltages which are used to maintain an identical trip point in each of a plurality of translator circuits. Generally, the trip point is set at midway between the "high" and the "low" levels of the incoming logic signal. The control voltages assure reliable performance over a wide operating environment.

Abstract: A BiCMOS voltage reference generator circuit generates and maintains a reference voltage within 3 mV over an 80.degree. C. temperture range and over a 1 volt change in power supply level. The circuit uses feedback from the output of the reference voltage generator to the current source supplying current to the voltage reference generator. This feedback increases the effective output impedance of the current source, making the reference voltage output substantially independent of power supply variations. The circuit operates with power supply differential as low as about 3 volts, and preferably is fabricated from bipolar transistors and MOS transistors on the same chip.

Abstract: A lightweight asphalt roofing product wherein the asphalt-based coating has a specific gravity less than 1.0. A lightweight filler is used which has an effective specific gravity in the range of 0.10-0.50 and is present in the coating in the range of 3%-25% by weight of the filled coating. In a preferred embodiment, the filler particles have hollow, gas filled inclusions, and comprise expanded perlite particles or expanded permicite particles.

Abstract: A signal translator for converting an input voltage (V.sub.I) into an output voltage (V.sub.O) at a different level contains a primary element stack (10) and a similarly-configured image element stack (12), both coupled between the sources of a potentially first variable supply voltage (V.sub.CC) and a normally constant second supply voltage (V.sub.EE). A reference voltage (V.sub.R) is supplied to both a primary-stack transistor (Q2) which provides the output voltage and an image-stack transistor (Q4) which provides a feedback signal (V.sub.F). A feedback circuit (14) formed with an amplifier (16) and a shifting circuit (18) response to the feedback signal to supply the reference voltage at such a value as to compensate the output voltage for changes in the first supply relative to the second supply voltage is particularly useful for CTL-to-TTL logic.

Abstract: The present invention is a thermometer used for measuring furnace temperaes in the range of about 1800.degree. to 2700.degree. C. The thermometer comprises a broadband multicolor thermal radiation sensor positioned to be in optical alignment with the end of a blackbody sight tube extending into the furnace. A valve-shutter arrangement is positioned between the radiation sensor and the sight tube and a chamber for containing a charge of high pressure gas is positioned between the valve-shutter arrangement and the radiation sensor. A momentary opening of the valve shutter arrangement allows a pulse of the high gas to purge the sight tube of air-borne thermal radiation contaminants which permits the radiation sensor to accurately measure the thermal radiation emanating from the end of the sight tube.

Abstract: A bipolar voltage translator contains a pair of differentially coupled transistors (Q1 and Q2) for converting an input voltage (V.sub.IN) supplied to one (Q1) of the pair into an output voltage (V.sub.OUT) taken between the other (Q2) and a first resistor (R9). A further transistor (Q4) coupled through a second resistor (R12) to a V.sub.EE supply provides current for the differential pair. A voltage reference circuit (10) containing at least three serially coupled diodes (S5, J3, and J4) with a resistive voltage divider (R13 and R14) across an intermediate one (J3) of the diodes provides the current-source transistor with a reference voltage (V.sub.REF2) that equals V.sub.EE +(1+.alpha.)V.sub.BE where .alpha. is 0.2-3.0. The ratio of the first resistor to the second is desirably .beta./.alpha. where .beta.is the output voltage swing divided by V.sub.BE. If .beta. is 1 and the transistors are NPN devices, the output voltage level is suitable for current tree logic.

Abstract: A hay rack top which is designed to fit on conventional hay rack enclosures or bunks in order to protect hay bales and hay placed in the enclosure from the elements, which includes multiple, shaped braces designed for clamping in spaced relationship to the top ring of a conventional hay rack and extending upwardly and inwardly to support a flexible cover secured on the arms of the braces by means of a draw string tightened around shoulders shaped in the braces. The braces are easily removed from the hay rack by loosening the clamps, and the top can be quickly and easily removed from the braces by loosening the draw string.

Abstract: The present invention concerns stacking of shingles, in particular shingles having one edge portion thicker than the other edge portion. Such shingles require that at least some of the shingles in a stack be oriented to place the thicker edge thereof opposite the thicker edge of the other shingles in the stack to form a neat and easily packaged stack of shingles. Such a stack of shingles must be formed quickly and accurately in order to keep up with the high rate of shingle production. The present invention accomplishes this by permitting selected shingles to be dropped and simultaneously rotated about a longitudinal axis as the shingles drop from one star wheel catcher (20) to another star wheel catcher (30). This rotation takes place by applying a substantial moment to the shingle as it falls by interposing specially shaped flipping fingers (46) in the path of the shingle.

Abstract: The present invention relates to apparatus for forming a series of shingles from two shingle members. In the past such apparatus has required an inordinate number of hand operations and warehousing of such shingle members. These hand operations and warehousing functions have resulted in a substantial number of non-conforming shingles, which must be rejected, and also causing other problems which affect the overall productivity of such prior art apparatus. The present invention anticipates forming from stock material a complete set of such shingle members, maintaining the shingle members in a set in a predetermined positional relationship throughout the manufacturing operation up to and including the formation of stacks of shingles formed thereby. When such a set of shingle members includes a pair of overlay portions formed of interdigitated tabs, the present invention permits these tabs to be defined to form two styles of shingles.