Low-Power Modulation in an Amplifier

Abstract

A switching audio amplifier may include a modulation enhancement feature, in which the pulse-width modulated (PWM) signals driving the output stage are reduced or increased by identical step sizes to create an auxiliary PWM scheme representative of an idle (low-power) state of the input signal. The PWM signals, provided to a full-bridge power stage circuit for example, may be thereby reduced to another state to reduce power dissipation in a switch-mode power supply. By incrementally adjusting the PWM duty-cycle identically in all PWM signals to a value less than (or up to) 50%, the amount of current dissipated in the output load may be effectively controlled. The PWM pulses may be adjusted up or down, while checking for saturation corresponding to both minimum and maximum pulse-widths. A dampener circuit may be used to set the time between incremental adjustments, to further reduce audible pops and clicks.

Description

PRIORITY CLAIM

This application claims benefit of priority of U.S. provisional application Ser. No. 61/543,998 titled “Circuits and Methods Used in Audio Signal Processing”, filed Oct. 6, 2011, which is hereby incorporated by reference in its entirety as though fully and completely set forth herein.

FIELD OF THE INVENTION

The present invention relates generally to signal processing, and more particularly performing low-power modulation in an amplifier.

DESCRIPTION OF THE RELATED ART

Signal processing represents a combined application of electrical/computer engineering and mathematical principles, primarily directed to the analysis of and operation on either discrete or continuous time signals. Signals of interest can include sound, images, time-varying measurement values and sensor data, for example biological data such as electrocardiograms, control system signals, telecommunication transmission signals such as radio signals, and many others. Signals are typically analog and/or digital electrical representations of time-varying or spatial-varying physical quantities. Types of signal processing include analog, discrete time, and digital.

Analog signal processing is performed on signals that have not been digitized, for example signals that are used in classical radio, telephone, radar, and television systems. Analog signal processing typically makes use of linear electronic circuits such as passive filters, active filters, additive mixers, integrators and various types of delay lines, as well as non-linear circuits such as frequency mixers and voltage-controlled amplifiers, voltage-controlled filters, voltage-controlled oscillators and phase-locked loops. Discrete time signal processing is performed on sampled signals that are defined at discrete points in time, and as such are quantized in time, but not in magnitude. Analog discrete-time signal processing is based on electronic devices such as sample and hold circuits, analog time-division multiplexers, analog delay lines and analog feedback shift registers, and may be considered a predecessor of digital signal processing.

Digital signal processing involves the processing of digitized discrete-time sampled signals. Processing is typically performed by general-purpose computers or digital circuits such as application specific integrated circuits (ASICs), field-programmable gate arrays, or specialized digital signal processors (DSPs). Digital signal processing mostly includes performing arithmetic operations such as fixed-point and floating-point operations, real-valued and complex-valued operations, multiplication and addition. Many of these operations are implemented through the use of circular buffers and look-up tables. Examples of digital signal processing algorithms include Fast Fourier transforms (FFT), finite impulse response (FIR) filters, infinite impulse response (IIR) filters, and adaptive filters such as the Wiener and Kalman filters.

Audio signal processing, sometimes referred to as audio processing, is the processing of electrical signals that correspond to auditory signals, or sound. Since audio signals may be electronically represented in either digital or analog format, audio signal processing may also take place in either the analog or digital domain. In analog audio signal processing, operations are performed directly on the electrical signals corresponding to the audio signals, while digital signal processing consists mostly of mathematical operations performed on digital representations of the electrical signals that correspond to respective audio signals. Typically, the digital representation of audio signals expresses the pressure waveform that characterizes the audio signal as a sequence of binary numbers. This permits signal processing using digital circuits such as microprocessors and computers, and while analog to digital conversion can be prone to loss, most modern audio systems use the digital approach because digital signal processing techniques are overall more powerful and efficient than signal processing in the analog domain.

Overall, since audio signals first need to be converted to electrical signals, digital audio processing systems include both analog and digital components in a full processing path that begins with the pressure waveforms that physically define the audio signal and ends with the digital representation of the corresponding electrical signals derived therefrom. Some of the most common components typically used in audio processing systems include pulse-width modulators, power limiters, start-up circuits, power regulators, comparators, amplifiers, oscillators, among others. The quality and operating precision of these components directly impacts the quality of audio signal processing systems, as designers have to continually overcome numerous difficult design challenges to meet required specifications and quality standards.

SUMMARY

Various embodiments of an audio amplifier include circuitry to perform modulation enhancement. Specifically, a low-power modulation scheme may be implemented in an amplifier as a deterministic pulse-width modulation scheme by which the gate drive signals are eliminated at or near zero-crossing boundaries, to reduce power loss that may occur during switching and/or conduction, without introducing a transient in a power stage circuit of the audio amplifier. In some embodiments, the amplifier may be either a class-BD or a class-AD amplifier capable of accepting a bipolar input, where zero value inputs, referred to as mute or digital silence in audio systems, would normally be output through a pulse-width modulation (PWM) scheme in which the duty-cycle of the PWM signal is 50%, and both positive and negative PWM signals are equal. The modulation enhancement may include reducing or increasing the PWM signals (i.e. the duty-cycle value of the PWM signals) by identical step sizes (amounts) to create a fixed or deterministic pulse-width modulation scheme in the audio amplifier. The PWM signals provided to a full-bridge power stage circuit may thereby be reduced to another state, and may be used to reduce power dissipation, both switching and conducted, in a switch-mode power supply by reducing the PWM duty-cycle identically to a value less than 50%, which effectively controls the amount of current dissipated in the output load. Effectively, both the common-mode voltage and the difference-mode voltage may be reduced at the load to zero voltages through a modulation technique that eliminates the PWM pulses without introducing a transient in a power stage circuit.

The mechanism to reduce the duty-cycle values of the respective PWM signals may be implemented in hardware, software or a combination thereof. In one set of embodiments, the modulation enhancement may include an algorithm designed to autonomously enable a power savings mode in the audio amplifier based on certain specified, detectable parameters. The detectable parameters may include a mute signal, or a programmable audio level threshold to which the input audio level may be compared. The end value used for reducing the PWM duty-cycles (i.e. duty-cycle values) may be a programmable minimum pulse-width, or zero, which may eliminate the PWM pulses entirely. Elimination of the PWM pulses may help recover all switching and conduction losses in the power stage field effect transistors (FETs). Furthermore, the duty-cycles may be incrementally and simultaneously (concurrently) adjusted, with the increments corresponding to specified step sizes, to avoid transients and perturbations on the outputs, and significantly reduce audible pops and clicks. In some hardware implementations, a counter may be used to adjust the PWM pulses either up or down, while two comparators may check for saturation for both minimum and maximum pulse-widths. A dampener circuit may be used to set the time between step size adjustments, to further reduce audible pops and clicks.

Accordingly, a signal processing system (SPS) may be designed to include a signal processing circuit that receives an input signal, and generates a first control value representative of the input signal. The SPS may further include an auxiliary circuit that generates a second control value representative of an idle state of the input signal. A control circuit within the SPS may receive an input control value, and generate a control signal representative of the input signal according to the received input control value. A selection circuit may select and provide the first control value as the input control value to the control circuit, responsive to an indication that the input signal is not in the idle state, and it may select and provide the second control value as the input control value to the control circuit, responsive to an indication that the input signal is in the idle state. In case of a switching amplifier, for example, the first control value, the second control value, and the input control value all represent duty cycle values, where the control signal is a PWM signal having a duty cycle defined by the input control value.

The SPS may include an indicator circuit that generates an event signal indicative of whether or not the input signal is in the idle state. The indicator circuit may assert the event signal to indicate that the input signal has entered the idle state, in response to a mute button being pushed, the input signal falling below a specified level, or any other condition that may be specified as indicative of the input signal having entered an idle (or low-power state). The auxiliary circuit may gradually decrease the second control value over a time period of specified length until the second control value reaches a minimum value, responsive to an event indicating that the input signal has entered the idle state. Similarly, the auxiliary circuit may gradually increase the second control value over a time period of specified length until the second control value reaches a default value, responsive to an event indicating that the input signal has exited the idle state. In addition, the auxiliary circuit may hold the second control value at the default value for a time period of specified length before gradually decreasing the second control value, and also hold the second control value at the minimum value for a time period of specified length before gradually increasing the second control value. The specified length of each time period may be programmable.

In order to improve the output performance of switching amplifiers, a modulator may be designed for modifying an output signal representative of an input signal when the input signal is in an idle (or low-power) state. The modulator may include a selection circuit that receives a first control value representative of a present value of the input signal, and a second control value representative of the input signal being in the idle state. The selection circuit may provide the first control value as an input control value to a control circuit—which generates a control signal representative of the input signal according to the input control value—responsive to an indication that the input signal is not in an idle state. Responsive to an indication that the input signal is in the idle state, the selection circuit may provide the second control value as the input control value to the control circuit. An auxiliary circuit in the modulator may incrementally adjust the second control value until the second control value reaches a desired value, responsive to the input signal entering the idle state, or the input signal exiting the idle state.

The auxiliary circuit may incrementally adjust the second control value at specified rate to reach the desired value within a time period of desired length. This may include incrementally increasing the second control value from a minimum value to a default value, responsive to the input signal exiting the idle state, and incrementally decreasing the second control value from the default value to the minimum value, responsive to the input signal entering the idle state. When used in a switching amplifier, the first control value, the second control value, and the input control value may represent duty cycle values, and the control signal may be a PWM signal having a duty cycle defined by the input control value. In one embodiment, the default value represents a 50% duty cycle value. The minimum value, the default value, and the desired length of the time period may all be programmable values.

In some embodiments, the modulator includes an indicator circuit that generates an event signal indicative of the input signal entering and exiting the idle state, and provides the event signal to the auxiliary circuit. In such embodiments, the auxiliary circuit incrementally adjusts the second control value according to the event signal. The indicator circuit may assert the event signal to indicate that the input signal has entered the idle state, in response to an event, such as a button being pushed, the input signal falling below a specified level, or any other previously identified conditions. Upon detecting that the input signal has entered or exited the idle state, the auxiliary circuit may first hold the second control value at its present value for a time period of specified length before starting to incrementally adjust the second control value.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of embodiments of the present invention may be obtained when the following Detailed Description is considered in conjunction with the following drawings, in which:

FIG. 1 illustrates various exemplary systems or devices which may use the techniques described herein;

FIG. 2 is a block diagram of a portion of a system including a Class D amplifier;

FIG. 3 is an exemplary block diagram of an audio subsystem according to prior art;

FIG. 4 shows a partial block diagram of an audio subsystem in which power reduction during idle states is achieved by applying auxiliary pulse-width modulation (APWM) to the PWM signals;

FIG. 5 shows the circuit diagram of one embodiment of the auxiliary pulse-width modulator circuit of FIG. 4;

FIG. 6a shows the relevant pulses and waveforms for the audio subsystem shown in FIG. 4, with APWM enabled, and pulse reduction performed;

FIG. 6b shows the relevant pulses and waveforms for the audio subsystem shown in FIG. 4, with APWM disabled, and the pulse released; and

FIG. 6c shows in more detail the section of the waveforms shown in FIG. 6b that correspond to the pulse being released from a state where minimum pulse equals zero.

FIG. 7a shows the relevant pulses and waveforms illustrating the effect of pulse reduction on the common-mode voltage and the difference-mode voltage while the amplifier is configured in class-BD mode, for the audio subsystem shown in FIG. 4, with APWM enabled.

FIG. 7b shows the relevant pulses and waveforms illustrating the effect of pulse reduction on the common-mode voltage and the difference-mode voltage while the amplifier is configured in class-AD mode, for the audio subsystem shown in FIG. 4, with APWM enabled.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION

FIG. 1 illustrates exemplary systems, which may utilize the techniques described above. More specifically, FIG. 1 illustrates exemplary systems, which may utilize an audio subsystem, (which may include an amplifier such as a Class D amplifier), featuring various improvements. As shown, embodiments of the techniques disclosed herein may be used in any one ore more of various systems which involve the amplification of signals. For example, embodiments of the invention may be used in various systems that operate to amplify audio signals for provision to a loudspeaker for audible presentation. It is noted that the various terms or designations for circuits, such as “signal processing”, “auxiliary”, “control”, “indicator”, etc. are merely names or identifiers used to distinguish among these circuits, and these terms are not intended to connote any specific meaning

As shown, the exemplary systems may include a display device 102; an audio system 104, such as a stereo amplified docking station for a portable music player, CD player, etc.; or a telephone 106 and 108, such as a smart phone, e.g., an iPHONE™ or other similar type of smart phone. It should be noted that FIG. 1 is provided by way of example, and is by no means intended to be exhaustive. Accordingly, various embodiments disclosed herein may equally be used in other applications and systems not shown in FIG. 1, where limiting the output power is desired.

FIG. 2 illustrates an example of an Audio subsystem 120 which may be present in the systems of FIG. 1. In one set of embodiments, audio subsystem may be an amplifier subsystem, which may more specifically be a class D amplifier subsystem. In one or more of the devices of FIG. 1, at least one Audio subsystem 120 may be present in the audio output section of the device, and more specifically in the amplifier portion of the audio section of the device. As shown in FIG. 2, an audio input signal 118 may be received at an input to the Audio subsystem 120. The Audio subsystem 120 receives the audio input signal 118 and operates to amplify the received audio input signal to produce amplified audio output signal 122. The amplified audio output signal 122 may then be provided to loudspeaker 124 for audible presentation.

FIG. 3 is an exemplary block diagram of an audio subsystem (which, in some embodiments, may be one implementation of a Class D amplifier), according to prior art. As shown in FIG. 3, the audio subsystem comprises an input that receives digital audio data, which is an N-bit pulse code modulated (PCM) input signal. The audio subsystem also includes a digital signal processor, referred to as Audio Signal Processor ASP 202, which receives the input signal and generates output data that is configured for use in generating a pulse train driver signal that corresponds to the input signal. The ASP 202 receives the N-bit input signal, and generates an M-bit output, which is provided to a Digital PWM (Pulse Width Modulator) block 204.

The Digital PWM block 204 includes a PWM Controller 212, two PWM driver blocks labeled PWM0 (232) and PWM1 (234), and may contain other logic as well. The PWM Controller 212 calculates edge locations of the pulse train to be generated, and produces two (M−1)-bit outputs. In particular, each of the two (M−1)-bit outputs may represent respective edges of pulses to be generated. The two (M−1)-bit outputs are used by individual pulse width modulators PWM0 and PWM1 to produce the final differential PWM outputs PWM_OUTP and PWM_OUTN. In general, PWM block 204 may comprise a small signal-processing block that operates on the M-bit input data and separates the M-bit input data into two individual streams of M−1 bits each. These (M−1)-bit streams may be independent, or, more specifically, they may have some correlation to each other, while the actual data may differ on an instantaneous pulse-by-pulse basis.

Block 222 comprises logic for handling dead time, as well as a MOSFET Power Output Stage and gate drivers for controlling the MOSFET Power Output Stage. The MOSFET Power Output Stage portion of block 222 may include high power switches, preferably MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The high power switches generate a high-power (amplified) replica of the received pulse train. The MOSFET Power Output Stage portion provides the amplified pulse train to low pass filter 224. As shown, the Output Stage provides a differential pair of output signals, referred to as OUTP and OUTN, which provide two differential pulses per PWM period. The low pass filter 224 performs a low pass filter operation on the differential pulses and provides the two outputs, referred to as OUTP_FILT and OUTN_FILT, to a load, e.g., to a loudspeaker 124.

Low Power Modulation Scheme in an Amplifier

In one set of embodiments, an auxiliary modulation scheme in an amplifier may be used to deterministically generate pulse-widths at or near zero crossings to reduce power loss in the audio amplifier. Consequently, power dissipation may be reduced in switch-mode power supplies, which may be built into audio systems such as the audio system shown in FIG. 3. These audio systems may themselves be part of consumer electronics devices, such as those shown in FIG. 1, for example. Power dissipation may therefore be reduced in systems featuring H-Bridge circuits, such as the MOSFET output stage in block 222 of FIG. 3. H-Bridge circuits are well known in the art, and are not explicitly shown for the sake of simplicity. The contribution to power loss in the system is dominated by the losses due to switching the power MOSFETs in the H-Bridge configuration, and is further dominated by the loss in power devices such as the inductor in the output stage. In one set of embodiments, power reduction during idle states may be achieved by bypassing the audio input and then applying a modulation scheme to the PWM signals PWM_OUTN and PWM_OUTP. While the aforementioned devices and circuits may benefit from power reduction performed in the manner that will be further described below, it should also be noted that many other systems and circuits—similar to the audio systems and H-Bridge circuits mentioned above—may benefit from similarly performed power reduction, even if such systems are not explicitly discussed herein.

In an audio system (such as the one shown in FIG. 3, for example) where the input audio signal is bipolar or centered around zero, a digital mute condition may be interpreted as corresponding to a mid-scale or 50% PWM duty-cycle. Therefore, during periods of inactive audio, the power devices in the MOSFET output stage (in block 222) may still be switching. In some cases, the frequency of the PWM output signals PWM_OUTN and PWM_OUTP may be reduced to a slower rate, to reduce the switching losses arising from the non-idealities associated with turning the power MOSFET devices on and off. In one set of embodiments, the difference-mode signal may be used to reduce the PWM pulse to a programmable final width. In some cases the final width may be a minimum pulse-width, while in other cases the final PWM duty-cycle might be zero. In the case where the duty-cycle is zero, the PWM pulse may be eliminated entirely.

FIG. 4 shows an audio subsystem in which power reduction during idle states is achieved by applying auxiliary pulse-width modulation (APWM) to the PWM signals. As previously mentioned, ASP 202, receives the input signal and generates output data that is configured for use in generating a pulse train driver signal that corresponds to the input signal. That is, the ASP 202 receives the N-bit input signal, and generates an M-bit output, which is representative of the audio input signal. However, instead of providing this representative M-bit output signal directly to PWM controller 204, the signal is provided to a summation engine 402, as shown in FIG. 4. An auxiliary pulse-width modulator circuit 404 may generate a low-power mode duty-cycle value to be applied to the PWM signals, and the auxiliary duty-cycle value may be selected using summation engine 402, to be provided to PWM controller 212 during idle states, or low power. That is, when the Low-Power Mode select signal is asserted, the output from circuit 404 may be selected as the input of summation engine 402 to be provided through the output of summation engine 402 to PWM circuit 204. In one embodiment, summation engine 402 may be a multiplexer which selects its output as either a signal derived from the audio input or the value provided by auxiliary pulse-width modulator (APWM) 404. It should also be noted that the auxiliary duty-cycle value may be arithmetically summed with the audio input over time to achieve the same effect, without the use of a multiplexer, as long as the difference-mode voltage averaged to zero over one PWM period.

Auxiliary pulse-width modulator 404 may reduce or increase the duty-cycle value for PWM_OUTP and PWM_OUTN by identical increments or step sizes/amounts to create the auxiliary pulse-width difference-mode voltage modulation scheme. The PWM signals provided to a full-bridge power stage circuit in block 222 may be reduced to another state, and may be used to reduce power dissipation by reducing the PWM duty-cycle identically to a value less than 50%, which effectively controls the amount of current dissipated in the output load, in this case speaker 124. In this embodiment, the input (i.e. audio input signal 118) does not affect the output during idle/low power states, effectively bypassing active modulation in mute mode. Accordingly, the Low-Power Mode Select signal may be, for example, a mute signal, which may be asserted to select the APWM duty-cycle value as opposed to the modulated output generated by signal processor 202. It should be noted again that the auxiliary PWM scheme may be equally applied to other systems, and the live, or modulated input provided to summation engine 402—as the second input opposite of the APWM duty-cycle value—may represent a PWM duty-cycle value representative of any desired type of signal, not only an audio signal.

Auxiliary pulse-width modulator 404 may be implemented in hardware, software or a combination of the two. In one set of embodiments, the audio subsystem in FIG. 4 may implement an algorithm designed to autonomously enable a power savings mode based on certain detectable parameters, which may include a mute signal, or a programmable audio level threshold to which the input audio level may be compared. That is, Low-Power Mode Select signal may be generated in a variety of ways, one of which may be a mute signal asserted directly (e.g. as a result of a mute button being pushed), or it may be generated as representative of certain conditions in the system being met. For example, the level of the input (audio) signal may be compared to a programmable threshold level, and the input signal falling below the threshold, such as a level measured in dB, decibel, may result in the assertion of the Low-Power Mode Select signal. In one set of embodiments, an algorithm may be implemented in audio signal processor 202, or some other element (not shown), to generate the Low-Power Mode Select signal to select the appropriate PWM duty-cycle values to be provided to PWM controller 212. The end value to which the PWM duty-cycle values are reduced may be a programmable minimum pulse-width, or zero, which may eliminate the PWM pulses entirely. Elimination of the PWM pulses may help recover all switching and conduction losses in the power stage MOSFETs (in block 222), and the duty-cycle values may be concurrently adjusted incrementally, with the increments corresponding to specified step sizes, to avoid transients and perturbations on the output signals OUTP_FILT and OUTN_FILT, and therefore significantly reduce audible pops and clicks in loud speaker 124.

FIG. 5 shows the circuit diagram of one embodiment of the auxiliary pulse-width modulator circuit 404. As shown in FIG. 5, a counter 504 is used to adjust the PWM pulses either up or down, while two comparators 512 and 514 check for saturation for both minimum and maximum pulse-width values. A dampener circuit 502 is used to set the time between step size adjustments, to further reduce audible pops and clicks. By controlling the time between adjustments, a desired “ramping” or “damping” of the signal may be achieved as desired. Control circuit (Control Logic) 506 may arbitrate starts and stops of counter 504. Accordingly, counter 504 may be operated to calculate/provide the desired PWM duty-cycle values. In order to reduce the duty-cycle value, the counter 504 may count down from a 50% duty-cycle state. The final value for counter 504—that is, the value counter 504 is expected to reach—may be programmed as either a minimum duty-cycle value, or counter 504 may eliminate the pulse (i.e. outputs PWM_OUTP and/or PWM_OUTN produced by digital PWM block 204, for example) entirely by reaching a count value of zero (0). Conversely, when releasing the PWM from the idle/low-power state, counter 504 may count up from the minimum duty-cycle value (which may be zero) to 50%. Furthermore, as mentioned above, additional counter 502 may be operated to determine the slew rate for the pulse reduction and pulse release. The time constant value may be programmed into counter 502 in order to obtain specific, desired slew rates.

FIG. 6a shows the relevant pulses and waveforms (for example for the audio subsystem shown in FIG. 4) when APWDM is enabled, and pulse reduction is performed. As shown in FIG. 6a, the Start Event represents the system entering an idle, or low-power state, which may take place as previously described, either through the pressing of a mute button, or the input signal meeting certain conditions, among others. Signals A and B represent the signals that would be produced by PWM block 204 according to the duty-cycle values provided by signal processor 202. Signals C and D represent the signals generated by PWM block 204 according to the duty-cycle values provided by APWM block 404. As previously mentioned, a digital mute condition may be interpreted as corresponding to a mid-scale or 50% PWM duty-cycle by processing block 202, which therefore generates the corresponding duty-cycle value of 50%, leading to input derived output signals A and B.

Referring back to FIG. 5, upon the Start Event, control logic 506 may assert the start signal to counters 502 and 504, which may begin counting in specified increments. FIG. 6a provides an example where counter 504 begins counting down, as instructed by Up/Down signal from control unit 506. Counter 504 may count down each time the Inc/Dec signal is asserted by counter 502 according to the time constant value programmed into 502 by control unit 506. Counter 504 may begin counting down from a value representative of a 50% PWM duty-cycle value, and outputting the APWM duty-cycle value according to which output signals C and D are generated. From that point on, each successive value output by counter 504 is smaller according to the specified decrement by which counter 504 is counting down, shown in FIG. 6a simply as units of one (1). As shown in FIG. 6a, the scaled pulses in output signals C and D are becoming narrower and narrower, eventually reaching a minimum pulse-width. The output of comparator 514 is asserted when the minimum pulse-width has been reached, to instruct control unit 506 to stop the count. Accordingly, control unit 506 asserts the Stop signal to counter 504, which stops counting, maintaining the APWM duty-cycle value corresponding to the minimum pulse-width until the system exits the idle, or low-power mode. This period is shown in FIG. 6a as “T dampener”.

FIG. 6b shows the relevant pulses and waveforms when APWM is disabled, and the pulse is released. As shown in FIG. 6b, the Start Event represents the system exiting an idle, or low-power state, which may take place as previously described, either through the releasing of a mute button, or the input signal meeting certain conditions, for example exceeding a certain threshold value. Signals A and B again represent the signals that would be produced by PWM block 204 according to the duty-cycle values provided by signal processor 202. Signals C and D again represent the scaled signals generated by PWM block 204 according to the duty-cycle values provided by APWM block 404.

Upon the Start Event, control logic 506 may assert the start signal to counters 502 and 504, which may begin counting in specified increments. FIG. 6b provides an example where counter 504 begins counting up, as instructed by Up/Down signal from control unit 506. Counter 504 may count up each time the Inc/Dec signal is asserted by counter 502 according to the time constant value programmed into 502 by control unit 506. Counter 504 may begin counting up from a value representative of the minimum pulse duty-cycle value, and outputting the APWM duty-cycle value according to which output signals C and D are generated. As seen in FIG. 6b, during the time period “T dampener”, the output signal remains at the minimum pulse width. During this period, counter 502 does not assert the Inc/Dec signal to counter 504. Once the end of the “T dampener” period is reached, the Inc/Dec signal to counter 504 is asserted, and each successive value output by counter 504 is greater according to the specified increment by which counter 504 is counting up, shown in FIG. 6b as simple units of one (1). As shown in FIG. 6b, the scaled pulses in output signals C and D become wider and wider, eventually reaching a maximum pulse-width corresponding to a 50% duty-cycle value. The output of comparator 514 is asserted when the maximum pulse-width has been reached, to instruct control unit 506 to stop the count. Accordingly, control unit 506 asserts the Stop signal to counter 504, which stops counting, maintaining its APWM output corresponding to the 50% duty-cycle value. FIG. 6c shows the waveforms during pulse release in more detail.

FIG. 7a shows the relevant pulses and waveforms when APWM is enabled as previously described in FIG. 6a, and pulse reduction, and in this case pulse elimination is performed. The waveforms shown in FIG. 7a illustrate how APWM affects both the common-mode voltage and the difference-mode voltage at the loads (i.e. at the speakers) in an amplifier configured as a class-BD modulator driving an H-Bridge power stage. As shown in FIG. 7a, the APWM does not alter the difference mode-voltage (0V) while ramping the common-mode voltage to 0V. The input derived PWM outputs are shown as signals C and D in FIG. 7a. Once APWM is enabled, as previously described, the APWM overrides the input derived PWM outputs with actual (scaled) signals C′ and D′, which are identical in pulse-widths as shown in FIG. 7a. The amplifier PWM pulse-widths diminish at identical dimensions with identical timing, and therefore, APWM achieves both power and thermal savings by eliminating the PWM outputs of the amplifier.

FIG. 7b shows the relevant pulses and waveforms when APWM is enabled as previously described in FIG. 6a, and pulse reduction, and in this case pulse elimination is performed. The waveforms shown in FIG. 7b illustrate how APWM affects both the common-mode voltage and the difference-mode voltage at the loads in an amplifier configured as a class-AD modulator driving an H-Bridge power stage. As shown in FIG. 7b, the input derived class-AD PWM outputs, shown as signals C and D, are overridden with the actual (scaled) PWM outputs, shown as C′ and D′ in FIG. 7b. As also seen in FIG. 7b, the APWM asserts identical pulse-widths offset by 180 degrees, and the difference mode voltage still averages to 0V over one PWM period. Therefore, there is no audible transient at the load. Ultimately, APWM ramps the difference-mode voltage waveform to a DC value of 0V, and the DC common-mode voltage to 0V. The amplifier pulse-widths diminish at identical dimensions with identical timing, and therefore, APWM achieves both power and thermal savings by eliminating the PWM outputs of the amplifier.

According to at least the embodiments presented above, a method for generating an (amplified) output signal with reduced or eliminated transients may include receiving an input signal, generating a first control value representative of the input signal, generating a second control value representative of an idle state of the input signal, receiving (in a control circuit) an input control value, and generating a control signal representative of the input signal according to the received control value. Upon receiving an indication of whether or not the input signal is in the idle state, the first control value may be selected and provided as the input control value to the control circuit, if the indication is of the input signal not being in the idle state. If the indication is of the input signal being in the idle state, the second control value may be selected and provided as the input control value to the control circuit.

In one set of embodiments, the first control value, the second control value, and the input control value are duty cycle values, and the control signal is a pulse width modulated (PWM) signal having a duty cycle represented by the input control value. Furthermore, the PWM signal may be used to drive a switching power stage of an audio amplifier to produce an amplified output representative of the input signal. In some embodiments, an event signal may be generated as the indication of whether or not the input signal is in the idle state. The event signal may be asserted to provide the indication that the input signal has entered the idle state in response to a mute button being pushed, or the input signal falling below a specified level.

The method may further include gradually decreasing the second control value over a first time period of specified length until the second control value reaches a minimum value, responsive to the event indicating that the input signal has just entered the idle state. The second control value may also be gradually increased over a second time period of specified length until the second control value reaches a default value, responsive to the event indicating that the input signal has just exited the idle state. In both cases, upon detecting the event indicating entry into or exit from the idle state, the second control value may be held (at the default value and minimum value, respectively) for a specified, programmable time period prior to gradually decreasing or gradually increasing the second control value.

Although the embodiments above have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

1. A signal processing system comprising:

a signal processing circuit configured to receive an input signal, and generate a first control value representative of the input signal;

an auxiliary circuit configured to generate a second control value representative of an idle state of the input signal;

a control circuit configured to receive an input control value and generate a control signal representative of the input signal according to the received input control value; and

a selection circuit configured to select and provide: the first control value as the input control value to the control circuit, responsive to an indication that the input signal is not in the idle state; and the second control value as the input control value to the control circuit, responsive to an indication that the input signal is in the idle state.

2. The signal processing system of claim 1, wherein the first control value, the second control value, and the input control value represent duty-cycle values, and wherein the control signal is a pulse-width modulated (PWM) signal having a duty-cycle defined by the input control value.

3. The signal processing system of claim 1, further comprising:

an indicator circuit configured to generate an event signal indicative of whether or not the input signal is in the idle state.

4. The signal processing system of claim 3, wherein the indicator circuit is configured to assert the event signal to indicate that the input signal has entered the idle state, in response to one or more of:

a button being pushed; or

the input signal falling below a specified level.

5. The signal processing system of claim 1, wherein the auxiliary circuit is configured to perform one or more of:

gradually decrease the second control value over a time period of specified length until the second control value reaches a minimum value, responsive to an event indicating that the input signal has entered the idle state; or

gradually increase the second control value over a time period of specified length until the second control value reaches a default value, responsive to an event indicating that the input signal has exited the idle state.

6. The signal processing system of claim 5, wherein the auxiliary circuit is further configured to perform one or more of:

hold the second control value at the default value for a time period of specified length before gradually decreasing the second control value; or

hold the second control value at the minimum value for a time period of specified length before gradually increasing the second control value.

7. The signal processing system of claim 6, wherein the specified length of each time period is programmable.

8. The signal processing system of claim 6, wherein the first control value, the second control value, and the input control value represent duty-cycle values, and wherein the control signal is a pulse-width modulated (PWM) signal having a duty-cycle defined by the input control value;

wherein the default value represents a 50% duty-cycle value.

9. The signal processing system of claim 1, wherein the signal processing system is an amplifier, wherein the input signal is an audio signal, and wherein the output signal is an amplified version of the audio signal.

10. A method for generating an output signal without transients, the method comprising:

receiving an input signal, and generating a first control value representative of the input signal;

generating a second control value representative of an idle state of the input signal;

receiving in a control circuit an input control value, and generating a control signal representative of the input signal according to the received control value;

receiving an indication of whether or not the input signal is in the idle state;

selecting and providing the first control value as the input control value to the control circuit, if the indication is of the input signal not being in the idle state; and

providing the second control value as the input control value to the control circuit, if the indication is of the input signal being in the idle state.

11. The method of claim 10, wherein the first control value, the second control value, and the input control value are duty-cycle values, and wherein the control signal is a pulse-width modulated (PWM) signal having a duty-cycle represented by the input control value.

12. The method of claim 11, further comprising:

generating an output signal according to the control signal, wherein the output signal corresponds to the input signal.

13. The method of claim 12, wherein the input signal is an audio signal and the output signal is an amplified version of the input signal.

14. The method of claim 10, further comprising:

generating an event signal as the indication of whether or not the input signal is in the idle state.

15. The method of claim 14, wherein said generating the event signal comprises asserting the event signal to provide the indication that the input signal has entered the idle state, responsive to one or more of:

a button being pushed; or

the input signal falling below a specified level.

16. The method of claim 10, further comprising one or more of:

gradually decreasing the second control value over a first time period of specified length until the second control value reaches a minimum value, responsive to an event indicating that the input signal has just entered the idle state; or

gradually increasing the second control value over a second time period of specified length until the second control value reaches a default value, responsive to an event indicating that the input signal has just exited the idle state.

17. The method of claim 16, further comprising one or more of:

holding the second control value at the default value for a third time period of specified length subsequent to the event indicating that the input signal has just entered the idle state, prior to said gradually decreasing the second control value; or

holding the second control value at the minimum value for a fourth time period of specified length subsequent to the event indicating that the input signal has just exited the idle state, prior to said gradually increasing the second control value.

18. The method of claim 17, further comprising programming the specified length of each time period prior to:

said gradually decreasing the second control value;

said gradually increasing the second control value;

said holding the second control value at the default value; and

said holding the second control value at the minimum value.

19. The method of claim 17, wherein the first control value, the second control value, and the input control value represent duty-cycle values, and wherein the control signal is a pulse-width modulated (PWM) signal having a duty-cycle represented by the input control value;

wherein the default value represents a 50% duty-cycle value.

20. The method of claim 16, wherein said gradually decreasing the second control value comprises decreasing the second control value by a specified decrement value a specified number of times within the first time period.

21. The method of claim 16, wherein said gradually increasing the second control value comprises increasing the second control value by a specified increment value a specified number of times within the second time period.

22. A circuit for modifying an output signal representative of an input signal when the input signal is in an idle state, the circuit comprising:

a selection circuit configured to: receive a first control value representative of a present value of the input signal, and a second control value representative of the input signal being in the idle state; provide the first control value as an input control value to a control circuit, responsive to an indication that the input signal is not in an idle state, wherein the control circuit is configured to generate a control signal representative of the input signal according to the input control value; and provide the second control value as the input control value to the control circuit, responsive to an indication that the input signal is in the idle state; and

an auxiliary circuit configured to incrementally adjust the second control value until the second control value reaches a desired value, responsive to one or more of: the input signal entering the idle state; or the input signal exiting the idle state.

23. The circuit of claim 22, wherein the idle state represents a low-power state.

24. The circuit of claim 22, wherein the auxiliary circuit is configured to incrementally adjust the second control value at specified rate to reach the desired value within a time period of desired length.

25. The circuit of claim 24, wherein in incrementally adjusting the second control value, the auxiliary circuit is configured to perform one or more of:

incrementally increase the second control value from a minimum value to a default value, responsive to the input signal exiting the idle state; or

incrementally decrease the second control value from the default value to the minimum value, responsive to the input signal entering the idle state.

26. The circuit of claim 25, wherein the first control value, the second control value, and the input control value represent duty-cycle values;

wherein the control signal is a pulse-width modulated (PWM) signal having a duty-cycle defined by the input control value;

wherein the default value represents a 50% duty-cycle value.

27. The circuit of claim 25, wherein the minimum value, the default value, and the desired length of the time period are programmable.

28. The circuit of claim 22, further comprising:

an indicator circuit configured to generate an event signal indicative of the input signal entering and exiting the idle state, and provide the event signal to the auxiliary circuit;

wherein the auxiliary circuit configured to incrementally adjust the second control value according to the event signal.

29. The circuit of claim 28, wherein the indicator circuit is configured to assert the event signal to indicate that the input signal has entered the idle state, in response to one or more of:

a button being pushed; or

the input signal falling below a specified level.

30. The circuit of claim 22, wherein the auxiliary circuit is further configured to hold the second control value at its present value for a time period of specified length before starting to incrementally adjust the second control value, responsive to one or more of:

the input signal entering the idle state; or

the input signal exiting the idle state.