Abstract: In one aspect, a system includes a device controller, processing clusters, and processing elements. The device controller includes a device event status register configured to store bits corresponding to (i) a global event signal provided by an external source and (ii) a device event signal provided by a device event control register. A processing cluster includes a cluster event register configured to store bits corresponding to (i) the global event signal provided by the external source, (ii) the device event signal provided by the device event control register, and (iii) a cluster event signal. A processing element includes an element event register configured to store bits corresponding to (i) the global event signal provided by the external source, (ii) the device event signal provided by the device event control register, (iii) the cluster event signal provided by the cluster event register, and (iv) a processing element event signal.

Abstract: Systems and methods to route packets of information within an integrated circuit, across one or more boards, racks, blades, and/or chassis, and/or across a connected network of packet processing engines include various modes of operation. Packets are routed to their destination, for example an individual packet processing engine. The packets of information include address-mode indicators, one or more destination port indicators, and/or (long-distance) addresses.

Abstract: A drinking cup lid is disclosed. The drinking cup lid includes a body with a deck and an annular wall that depends downwards. The annular wall is adapted to insert into a drinking cup. A first gasket and a second gasket extend outward from the annular wall and are configured for sealing engagement with the drinking cup. A closure is pivotally attached to the annular wall and configured and arranged to pivot between a closed position, sealing the drinking cup closed, and an open position, opening the drinking cup.

Abstract: A cooking pan apparatus, system, and method of use, comprising: a drain opening in a side wall of the pan; and a pan handle attached to the side wall, comprising a hollow drain channel enclosing the drain opening and running from proximate the drain opening to a drain exit proximate a distal end of the pan handle.

Abstract: Systems and methods to implement a platform for processing streams of information, in particular quantification information such as, e.g., real-time sensor data, allow users to define algorithms that are evaluated and re-evaluated continuously as new information becomes available. Revenue received from users and/or other entities that are operating within the platform (or in conjunction with the platform) may be shared with the providers and/or publishers of the streams of information.

Abstract: Systems and methods to process packets of information using an on-chip processing system include a memory bank, an interconnect module, a controller, and one or more processing engines. The packets of information include a packet header and a packet payload. The packet header includes one or more operator codes. The transfer of individual packets is guided to a processing engine through the interconnect module and through the controller by operator codes included in the packets.

Abstract: A cooking pan apparatus, system, and method of use, comprising: a drain opening in a side wall of the pan; and a pan handle attached to the side wall, comprising a hollow drain channel enclosing the drain opening and running from proximate the drain opening to a drain exit proximate a distal end of the pan handle.

Abstract: Disclosed bone screws include multiple screw elements engaged together to provide the required strength along a longitudinal direction and the required flexibility in other degrees of freedom. The disclosed bone screws have a low profile. Further, the bone screws allow fine-tuning of the compression to be applied to bones or joints. Instrumentation for implanting and orienting the bone screws is also disclosed herein.

Abstract: A drinking cup lid is disclosed. The drinking cup lid includes a body with a deck and an annular wall that depends downwards. The annular wall is adapted to insert into a drinking cup. A first gasket and a second gasket extend outward from the annular wall and are configured for sealing engagement with the drinking cup. A closure is pivotally attached to the annular wall and configured and arranged to pivot between a closed position, sealing the drinking cup closed, and an open position, opening the drinking cup.

Abstract: A neural processing engine may perform processing within a neural processing system and/or artificial neural network. The neural processing engine may be configured to effectively and efficiently perform the type of processing required in implementing a neural processing system and/or an artificial neural network. This configuration may facilitate such processing with neural processing engines having an enhanced computational density and/or processor density with respect to conventional processing units.

Abstract: A drinking cup lid is disclosed. The drinking cup lid includes a body with a deck and an annular wall that depends downwards. The annular wall is adapted to insert into a drinking cup. A first gasket and a second gasket extend outward from the annular wall and are configured for sealing engagement with the drinking cup. A closure is pivotally attached to the annular wall and configured and arranged to pivot between a closed position, sealing the drinking cup closed, and an open position, opening the drinking cup.

Abstract: An arbitration mechanism provides quality of service guarantees for time-sensitive signals sharing a local area computer network with non-time-sensitive traffic. Device adapters are placed at all access points to an Ethernet network. The device adapters limit admission rates and control the timing of all packets entering the network. By doing so, collisions are eliminated for timesensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters. The time reference includes a frame with a plurality of phases. Each of the phases is assigned to a device adapter. Each device adapter is allowed to transmit packets of data onto the network only during the phase assigned thereto. The length of the phases may be modified in accordance with the number of packets to be transmitted by a particular device adapter. A master device adapter may be appointed to synchronize each of the device adapters.

Abstract: Systems and methods to process packets of information use an on-chip information processing system configured to receive, resolve, convert, and/or transmit packets of different packet-types in accordance with different protocols. A first packet-type may use a protocol for wired local-area-networking (LAN) technologies, such as Ethernet. A second packet-type may use a proprietary protocol. The proprietary protocol may be used to exchange information with one or more packet processing engines, such as neural processing engines.

Abstract: Systems and methods to route packets of information within an integrated circuit, across one or more boards, racks, blades, and/or chassis, and/or across a connected network of packet processing engines include various modes of operation. Packets are routed to their destination, for example an individual packet processing engine. The packets of information include address-mode indicators, one or more destination port indicators, and/or (long-distance) addresses.

Abstract: The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described.

Abstract: Systems and methods to process packets of information using an on-chip processing system include a memory bank, an interconnect module, a controller, and one or more processing engines. The packets of information include a packet header and a packet payload. The packet header includes one or more operator codes. The transfer of individual packets is guided to a processing engine through the interconnect module and through the controller by operator codes included in the packets.

Abstract: The subject matter disclosed herein provides methods, apparatus, and articles of manufacture for neural-based processing. In one aspect, there is provided a method. The method may include reading, from a first memory, context information stored based on at least one connection value; reading, from a second memory, an activation value matching the at least one connection value; sending, by a first processor, the context information and the activation value to at least one of a plurality of microengines to configure the at least one microengine as a neuron; and generating, at the at least one microengine, a value representative of an output of the neuron. Related apparatus, systems, methods, and articles are also described.

Abstract: A neural processing engine may perform processing within a neural processing system and/or artificial neural network. The neural processing engine may be configured to effectively and efficiently perform the type of processing required in implementing a neural processing system and/or an artificial neural network. This configuration may facilitate such processing with neural processing engines having an enhanced computational density and/or processor density with respect to conventional processing units.

Abstract: An arbitration mechanism provides quality of service guarantees for time-sensitive signals sharing a local area computer network with non-time-sensitive traffic. Device adapters are placed at all access points to an Ethernet network. The device adapters limit admission rates and control the timing of all packets entering the network. By doing so, collisions are eliminated for timesensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters. The time reference includes a frame with a plurality of phases. Each of the phases is assigned to a device adapter. Each device adapter is allowed to transmit packets of data onto the network only during the phase assigned thereto. The length of the phases may be modified in accordance with the number of packets to be transmitted by a particular device adapter. A master device adapter may be appointed to synchronize each of the device adapters.

Abstract: An arbitration mechanism provides quality of service guarantees for time-sensitive signals sharing a local area computer network with non-time-sensitive traffic. Device adapters are placed at all access points to an Ethernet network. The device adapters limit admission rates and control the timing of all packets entering the network. By doing so, collisions are eliminated for timesensitive traffic, thereby guaranteeing timely delivery. A common time reference is established for the device adapters. The time reference includes a frame with a plurality of phases. Each of the phases is assigned to a device adapter. Each device adapter is allowed to transmit packets of data onto the network only during the phase assigned thereto. The length of the phases may be modified in accordance with the number of packets to be transmitted by a particular device adapter. A master device adapter may be appointed to synchronize each of the device adapters.