Abstract: A novel hybrid band-pass filter is realized using semiconductor integrated hybrid technology, and includes two acoustic resonance units, and one IPD filter unit. The filter unit may be implemented as a high-pass filter, a low-pass filter, or a band-pass filter. The two acoustic resonance units and the IPD filter unit are arranged on a matching substrate, for example, by way of flip-chip technology and welding of electrodes, and a polymer filled shell is formed external to and surrounding the acoustic resonance units and the IPD filter unit to prevent oxidation and to maintain integrity of the weld points. The first acoustic resonance unit is connected with an input terminal of the IPD filter through a matching inductor, an output terminal of the IPD filter is connected with the second acoustic resonance unit through a matching inductor, and finally, the two acoustic resonance units and the IPD filter unit are integrated on the matching substrate.

Abstract: An acoustic resonator forms a component of an FBAR filter that includes a trap-rich layer to avoid parasitic conduction by degrading carrier lifetimes of a free charge carriers. The acoustic resonator has a first electrode, a second electrode disposed parallel to the first planar portion and a piezoelectric layer disposed between and contacting both the first and second planar electrodes. A silicon-based a support layer is bonded to the second electrode and includes a trap region. The acoustic resonator may be manufactured by (a) depositing the trap region on the support layer; (b) oxidizing a surface of the trap region; (c) depositing a bonding layer on the oxidized surface of the trap region; (d) bonding a first electrode to the bonding layer; (e) contacting a first side of a piezoelectric layer to the electrode; and (f) contacting a second side of the piezoelectric layer a second electrode.

Abstract: An acoustic resonator that has a first electrode with a first planar portion. A second electrode having a second planar portion is disposed parallel to the first planar portion. This second electrode has a bifurcated end that defines a gap. A piezoelectric layer is disposed between and contacts both the first planar portion and the second planar portion. Also contacting the piezoelectric layer is the bifurcated end of the second electrode. The gap is formed in the periphery of each resonator within a filter. It is formed in the top electrode, that is typically formed of molybdenum, but could be formed from other metals as well. Unlike a gap between a top electrode and piezoelectric material, the gap recited herein is entirely within the second electrode. This structure is compatible with an inner passivation layer that enables a single crystal piezoelectric layer and a larger bottom electrode.

Abstract: A method for fabricating an array of front ends for an array of packaged electronic components that each comprise: an electrical element packaged within a package comprising a front part of a package comprising an inner section with a cavity therein opposite the resonator defined by the raised frame and an outer section sealing said cavity; and a back part of the package comprising a back cavity in an inner back section, and an outer back section sealing the cavity, said back package further comprising a first and a second via through the back end around said at least one back cavity for coupling to front and back electrodes of the electronic component; the vias terminating in external contact pads that are coupleable in a ‘flip chip’ configuration to a circuit board; the method comprising the stages of: i. Obtaining a carrier substrate having an active membrane layer attached thereto by its rear surface, with a front electrode on the front surface of the active membrane layer; ii.

Abstract: A packaged electronic component comprising: an electronic component housed within a package comprising a front part of a package comprising an inner section with a front cavity therein opposite the electronic component defined by the raised frame and an outer section sealing said cavity; and a back part of the package comprising a back cavity in an inner back section, and an outer back section sealing the cavity, said back package further comprising a first and a second via through the back end around said at least one back cavity for coupling to front and back electrodes of the electronic component; the vias terminating in external contact pads adapted to couple the package in a flip chip configuration to a circuit board.

Abstract: A package for an electronic component, the package comprising a front end, a back end, and an active membrane layer sandwiched between front and back electrodes of conducting material; wherein front electrode has a surface that extends beyond an adjacent surface of the active membrane layer, the active membrane mechanically supported by the front end and covered by a back end comprising at least one back cavity having organic walls and lid of organic material, with filled through vias traversing the organic walls and lid for coupling to the electrodes by an internal routing layer; the vias being coupleable by external solderable bumps to a circuit board for coupling the package in a flip chip configuration.

Abstract: A package for an electronic component wherein the package comprises a front end, a back end, and an active membrane layer sandwiched between front and back electrodes of conducting material; the active membrane being mechanically supported by the front end and covered by a back end comprising at least one back cavity having organic walls and lid, with filled through vias traversing the organic lid and walls for coupling to the electrodes by an internal routing layer; the vias being coupleable by external solderable bumps to a circuit board for coupling the package in a ‘flip chip’ configuration.

Abstract: A method for fabricating an array of front ends for an array of packaged electronic components that each comprise: an electrical element packaged within a package comprising a front part of a package comprising an inner section with a cavity therein opposite the resonator defined by the raised frame and an outer section sealing said cavity; and a back part of the package comprising a back cavity in an inner back section, and an outer back section sealing the cavity, said back package further comprising a first and a second via through the back end around said at least one back cavity for coupling to front and back electrodes of the electronic component; the vias terminating in external contact pads that are coupleable in a ‘flip chip’ configuration to a circuit board; the method comprising the stages of: i. Obtaining a carrier substrate having an active membrane layer attached thereto by its rear surface, with a front electrode on the front surface of the active membrane layer; ii.

Abstract: A package for an electronic component wherein the package comprises a front end, a back end, and an active membrane layer sandwiched between front and back electrodes of conducting material; the active membrane being mechanically supported by the front end and covered by a back end comprising at least one back cavity having organic walls and lid, with filled through vias traversing the organic lid and walls for coupling to the electrodes by an internal routing layer; the vias being coupleable by external solderable bumps to a circuit board for coupling the package in a ‘flip chip’ configuration.

Abstract: A packaged electronic component comprising: an electrical element packaged within a package comprising a front part of a package comprising an inner section with a cavity therein opposite the resonator defined by the raised frame and an outer section sealing said cavity; and a back part of the package comprising a back cavity in an inner back section, and an outer back section sealing the cavity, said back package further comprising a first and a second via through the back end around said at least one back cavity for coupling to front and back electrodes of the electronic component; the vias terminating in external contact pads that are coupleable in a ‘flip chip’ configuration to a circuit board.

Abstract: A method of fabricating packaged electronic components with improved yield and at lower unit cost; the method comprising the steps of obtaining an active membrane layer on a carrier substrate, depositing a front electrode onto a front of the active membrane layer, obtaining an inner front section including at least a silicon handle or wafer, attaching an inner front end section to an outer surface of the front electrode, detaching the carrier substrate from a back surface of an active membrane on the opposite surface from the front surface on which the front electrode is deposited, patterning the active membrane layer into an array of at least one island of membrane, selectively removing the front electrode and bonding layer, selectively applying an inner passivation layer, and selectively depositing a back electrode layer on the thus exposed back surface of the active membrane.

Abstract: A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.

Abstract: A method of fabricating an FBAR filter device including an array of resonators, each resonator comprising a single crystal piezoelectric film sandwiched between a first metal electrode and a second metal electrode, wherein the first electrode is supported by a support membrane over an air cavity, the air cavity embedded in a silicon dioxide layer over a silicon handle, with through-silicon via holes through the silicon handle and into the air cavity, the side walls of said air cavity in the silicon dioxide layer being defined by perimeter trenches that are resistant to a silicon oxide etchant.

Abstract: An FBAR filter device comprising an array of resonators, each resonator comprising a single crystal piezoelectric layer sandwiched between a first and a second metal electrode, wherein the first electrode is supported by a support membrane over an air cavity, the air cavity being embedded in a silicon dioxide layer over a silicon handle, with through-silicon via holes through the silicon handle and into the air cavity, the side walls of said air cavity in the silicon dioxide layer being defined by barriers of a material that is resistant to silicon oxide etchants, and wherein the interface between the support membrane and the first electrode is smooth and flat.

Abstract: A piezoelectric resonator membrane having a thickness in the range of 200 nm to 500 nm wherein the thickness may be controlled to within 1%; the membrane being sandwiched between electrodes to create a resonator, wherein at least one of the electrodes comprises aluminum thereby minimizing damping due to the weight of the electrode.

Abstract: A single crystal membrane of BaxSr(1-x)TiO3 (BST) has been fabricated for the first time using molecular beam epitaxy. The membrane typically has a thickness of 200 nm to 500 nm and the thickness may be controlled to within 1%. It may be fabricated on a sapphire wafer carrier from which it may subsequently be detached. The smoothness of the membrane has an RMS of less than 1 nm. This membrane is very promising for the next generation of RF filters.

Abstract: 1.

Abstract: A chip socket defined by an organic matrix framework, wherein the organic matrix framework comprises at least one via post layer where at least one via through the framework around the socket includes at least one capacitor comprising a lower electrode, a dielectric layer and an upper electrode in contact with the via post.

Abstract: A method of fabricating an RF filter comprising an array of resonators, the method comprising the steps of: (a) Obtaining a removable carrier with release layer; (b) Growing a piezoelectric film on a removable carrier; (c) Applying a first electrode to the piezoelectric film; (d) Obtaining a backing membrane on a cover, with or without prefabricated cavities between the backing film and cover; (e) Attaching the backing membrane to the first electrode; (f) Detaching the removable carrier; (g) Measuring and trimming the piezoelectric film as necessary; (h) Selectively etching away the piezoelectric layer to fabricate discrete resonator islands; (i) Etching down through coatings backing membrane, silicon dioxide and into silicon handle to form trenches; (j) Applying passivation layer into the trenches and around the piezoelectric islands; (k) Depositing a second electrode layer over the dielectric and piezoelectric film islands; (l) Applying connections for subsequent electrical coupling to an interposer; (m)

Abstract: A method of fabricating an RF filter comprising an array of resonators comprising the steps of: Obtaining a removable carrier with release layer; Growing a piezoelectric film on a removable carrier; Applying a first electrode to the piezoelectric film; Obtaining a backing membrane on a cover, with or without prefabricated cavities between the backing film and cover; Attaching the backing membrane to the first electrode; Detaching the removable carrier; Measuring and trimming the piezoelectric film as necessary; Selectively etching away the piezoelectric layer to fabricate discrete resonator islands; Etching down through coatings and backing membrane to a silicon dioxide layer between the backing membrane and the cover to form trenches; Applying a passivation layer into the trenches and around the piezoelectric islands; Depositing a second electrode layer over the piezoelectric film islands and surrounding passivation layer; Applying connections for subsequent electrical coupling to an interposer; Selective