Patents by Inventor Dror Hurwitz
Dror Hurwitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10389331Abstract: A filter package comprising an array of piezoelectric films comprising an array of mixed single crystals that each comprise doped Aluminum Nitride, typically AlxGa(1-x)N or ScxAl(1-x)N, that is sandwiched between an array of lower electrodes and an array of upper electrodes comprising metal layers and silicon membranes with cavities thereover: the array of lower electrodes being coupled to an interposer with a first cavity between the array of lower electrodes and the interposer; the array of silicon membranes having a known thickness and attached over the array of upper electrodes with an array of upper cavities, each upper cavity between a silicon membrane of the array and a common silicon cover; each upper cavity aligned with a piezoelectric film, an upper electrode and silicon membrane, the upper cavities having side walls comprising SiO2; the individual piezoelectric films, their upper electrodes and silicon membranes thereover being separated from adjacent piezoelectric films, upper electrodes and silicType: GrantFiled: August 18, 2017Date of Patent: August 20, 2019Assignee: Zhuhai Crystal Resonance Technologies Co., LTD.Inventor: Dror Hurwitz
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Publication number: 20190245509Abstract: A method of fabricating an FBAR filter device including an array of resonators, each resonator comprising a single crystal piezoelectric film sandwiched between a first metal electrode and a second metal electrode, wherein the first electrode is supported by a support membrane over an air cavity, the air cavity embedded in a silicon dioxide layer over a silicon handle, with through-silicon via holes through the silicon handle and into the air cavity, the side walls of said air cavity in the silicon dioxide layer being defined by perimeter trenches that are resistant to a silicon oxide etchant.Type: ApplicationFiled: February 5, 2018Publication date: August 8, 2019Applicant: Zhuhai Crystal Resonance Technologies Co., Ltd.Inventor: Dror Hurwitz
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Publication number: 20190245515Abstract: An FBAR filter device comprising an array of resonators, each resonator comprising a single crystal piezoelectric layer sandwiched between a first and a second metal electrode, wherein the first electrode is supported by a support membrane over an air cavity, the air cavity being embedded in a silicon dioxide layer over a silicon handle, with through-silicon via holes through the silicon handle and into the air cavity, the side walls of said air cavity in the silicon dioxide layer being defined by barriers of a material that is resistant to silicon oxide etchants, and wherein the interface between the support membrane and the first electrode is smooth and flat.Type: ApplicationFiled: February 5, 2018Publication date: August 8, 2019Applicant: Zhuhai Crystal Resonance Technologies Co., Ltd.Inventor: Dror Hurwitz
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Patent number: 10236854Abstract: A method of fabricating a composite electronic structure for coupling an IC Chip to a substrate, the composite electronic structure comprising: at least one metal feature layer and at least one adjacent metal via layer, said layers being embedded in a dielectric comprising a polymer matrix and extending in an X-Y plane and having height, wherein the composite electronic structure further comprises, at least one capacitor coupled with at least one inductor, the at least one capacitor comprising a selected feature in a feature layer forming a lower electrode, and depositing a ceramic dielectric layer over said selected feature, applying a layer of photoresist, patterning the photoresist with a via post over said ceramic dielectric layer, sputtering a copper seed layer and electroplating copper into the pattern to form said via post over said ceramic dielectric layer, such that the ceramic dielectric layer is sandwiched between the selected feature layer and the via post, such that the via post stands on the cerType: GrantFiled: April 11, 2018Date of Patent: March 19, 2019Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.Inventors: Dror Hurwitz, Alex Huang
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Publication number: 20180367114Abstract: A method of fabricating a composite electronic structure for coupling an IC Chip to a substrate, the composite electronic structure comprising: at least one metal feature layer and at least one adjacent metal via layer, said layers being embedded in a dielectric comprising a polymer matrix and extending in an X-Y plane and having height, wherein the composite electronic structure further comprises, at least one capacitor coupled with at least one inductor, the at least one capacitor comprising a selected feature in a feature layer forming a lower electrode, and depositing a ceramic dielectric layer over said selected feature, applying a layer of photoresist, patterning the photoresist with a via post over said ceramic dielectric layer, sputtering a copper seed layer and electroplating copper into the pattern to form said via post over said ceramic dielectric layer, such that the ceramic dielectric layer is sandwiched between the selected feature layer and the via post, such that the via post stands on the cerType: ApplicationFiled: April 11, 2018Publication date: December 20, 2018Applicant: Zhuhai Advanced Chip Carriers & Electronic Substra te Solutions Technologies Co. Ltd.Inventors: Dror Hurwitz, Alex Huang
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Patent number: 10153750Abstract: A filter package comprising an array of piezoelectric films sandwiched between lower electrodes and an array of upper electrodes covered by an array of silicon membranes with cavities thereover: the lower electrode being coupled to an interposer with a first cavity between the lower electrodes and the interposer; the array of silicon membranes having a known thickness and attached over the upper electrodes with an array of upper cavities, each upper cavity between a silicon membrane of the array and a common silicon cover; each upper cavity aligned with a piezoelectric film, an upper electrode and silicon membrane, the upper cavities having side walls comprising SiO2; the individual piezoelectric films, their upper electrodes and silicon membranes thereover being separated from adjacent piezoelectric films, upper electrodes and silicon membranes by a passivation material.Type: GrantFiled: April 24, 2017Date of Patent: December 11, 2018Assignee: ZHUHAI CRYSTAL RESONANCE TECHNOLOGIES CO., LTD.Inventor: Dror Hurwitz
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Patent number: 10141912Abstract: A filter package comprising an array of piezoelectric films sandwiched between an array of upper electrodes and lower electrodes: the individual piezoelectric films and the upper electrodes being separated by a passivation material; the lower electrode being coupled to an interposer with a first cavity between the lower electrodes and the interposer; the filter package further comprising a silicon wafer of known thickness attached over the upper electrodes with an array of upper cavities between the silicon wafer and a silicon cover; each upper cavity aligned with a piezoelectric film in the array of piezoelectric films, the upper cavities having side walls comprising the passivation material.Type: GrantFiled: March 24, 2017Date of Patent: November 27, 2018Assignee: ZHUHAI CRYSTAL RESONANCE TECHNOLOGIES CO., LTD.Inventor: Dror Hurwitz
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Publication number: 20180278231Abstract: A filter package comprising an array of piezoelectric films comprising an array of mixed single crystals that each comprise doped Aluminum Nitride, typically AlxGa(1-x)N or ScxAl(1-x)N, that is sandwiched between an array of lower electrodes and an array of upper electrodes comprising metal layers and silicon membranes with cavities thereover: the array of lower electrodes being coupled to an interposer with a first cavity between the array of lower electrodes and the interposer; the array of silicon membranes having a known thickness and attached over the array of upper electrodes with an array of upper cavities, each upper cavity between a silicon membrane of the array and a common silicon cover; each upper cavity aligned with a piezoelectric film, an upper electrode and silicon membrane, the upper cavities having side walls comprising SiO2; the individual piezoelectric films, their upper electrodes and silicon membranes thereover being separated from adjacent piezoelectric films, upper electrodes and silicType: ApplicationFiled: August 18, 2017Publication date: September 27, 2018Inventor: Dror Hurwitz
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Publication number: 20180278227Abstract: A method of fabricating an RF filter comprising an array of resonators, the method comprising the steps of: (a) Obtaining a removable carrier with release layer; (b) Growing a piezoelectric film on a removable carrier; (c) Applying a first electrode to the piezoelectric film; (d) Obtaining a backing membrane on a cover, with or without prefabricated cavities between the backing film and cover; (e) Attaching the backing membrane to the first electrode; (f) Detaching the removable carrier; (g) Measuring and trimming the piezoelectric film as necessary; (h) Selectively etching away the piezoelectric layer to fabricate discrete resonator islands; (i) Etching down through coatings backing membrane, silicon dioxide and into silicon handle to form trenches; (j) Applying passivation layer into the trenches and around the piezoelectric islands; (k) Depositing a second electrode layer over the dielectric and piezoelectric film islands; (l) Applying connections for subsequent electrical coupling to an interposer; (m)Type: ApplicationFiled: March 24, 2017Publication date: September 27, 2018Inventor: Dror Hurwitz
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Publication number: 20180278228Abstract: A method of fabricating an RF filter comprising an array of resonators comprising the steps of: Obtaining a removable carrier with release layer; Growing a piezoelectric film on a removable carrier; Applying a first electrode to the piezoelectric film; Obtaining a backing membrane on a cover, with or without prefabricated cavities between the backing film and cover; Attaching the backing membrane to the first electrode; Detaching the removable carrier; Measuring and trimming the piezoelectric film as necessary; Selectively etching away the piezoelectric layer to fabricate discrete resonator islands; Etching down through coatings and backing membrane to a silicon dioxide layer between the backing membrane and the cover to form trenches; Applying a passivation layer into the trenches and around the piezoelectric islands; Depositing a second electrode layer over the piezoelectric film islands and surrounding passivation layer; Applying connections for subsequent electrical coupling to an interposer; SelectiveType: ApplicationFiled: April 24, 2017Publication date: September 27, 2018Applicant: Crystal Waves LABs LimitedInventor: Dror Hurwitz
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Publication number: 20180278236Abstract: A filter package comprising an array of piezoelectric films sandwiched between lower electrodes and an array of upper electrodes covered by an array of silicon membranes with cavities thereover: the lower electrode being coupled to an interposer with a first cavity between the lower electrodes and the interposer; the array of silicon membranes having a known thickness and attached over the upper electrodes with an array of upper cavities, each upper cavity between a silicon membrane of the array and a common silicon cover; each upper cavity aligned with a piezoelectric film, an upper electrode and silicon membrane, the upper cavities having side walls comprising SiO2; the individual piezoelectric films, their upper electrodes and silicon membranes thereover being separated from adjacent piezoelectric films, upper electrodes and silicon membranes by a passivation material.Type: ApplicationFiled: April 24, 2017Publication date: September 27, 2018Applicant: Crystal Waves LABs LimitedInventor: Dror Hurwitz
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Publication number: 20180274127Abstract: A single crystal membrane of BaxSr(1-x)TiO3 (BST) has been fabricated for the first time using molecular beam epitaxy. The membrane typically has a thickness of 200 nm to 500 nm and the thickness may be controlled to within 1%. It may be fabricated on a sapphire wafer carrier from which it may subsequently be detached. The smoothness of the membrane has an RMS of less than 1 nm. This membrane is very promising for the next generation of RF filters.Type: ApplicationFiled: March 24, 2017Publication date: September 27, 2018Applicant: Crystal Waves LABs LimitedInventor: Dror Hurwitz
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Publication number: 20180278233Abstract: A piezoelectric resonator membrane having a thickness in the range of 200 nm to 500 nm wherein the thickness may be controlled to within 1%; the membrane being sandwiched between electrodes to create a resonator, wherein at least one of the electrodes comprises aluminum thereby minimizing damping due to the weight of the electrode.Type: ApplicationFiled: March 24, 2017Publication date: September 27, 2018Inventor: Dror Hurwitz
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Publication number: 20180275485Abstract: 1.Type: ApplicationFiled: August 17, 2017Publication date: September 27, 2018Inventor: Dror Hurwitz
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Publication number: 20180278234Abstract: A filter package comprising an array of piezoelectric films sandwiched between an array of upper electrodes and lower electrodes: the individual piezoelectric films and the upper electrodes being separated by a passivation material; the lower electrode being coupled to an interposer with a first cavity between the lower electrodes and the interposer; the filter package further comprising a silicon wafer of known thickness attached over the upper electrodes with an array of upper cavities between the silicon wafer and a silicon cover; each upper cavity aligned with a piezoelectric film in the array of piezoelectric films, the upper cavities having side walls comprising the passivation material.Type: ApplicationFiled: March 24, 2017Publication date: September 27, 2018Inventor: Dror Hurwitz
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Patent number: 10014843Abstract: A composite electronic structure comprising at least one feature layer and at least one adjacent via layer, said layers extending in an X-Y plane and having height z, wherein the structure comprises at least one capacitor coupled in series or parallel to at least one inductor to provide at least one filter; the at least one capacitor being sandwiched between the at least one feature layer and at least one via in said at least adjacent via layer, such that the at least one via stands on the at least one capacitor, and the at least one of the first feature layer and the adjacent via layer includes at least one inductor extending in the XY plane.Type: GrantFiled: August 8, 2013Date of Patent: July 3, 2018Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.Inventors: Dror Hurwitz, Alex Huang
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Patent number: 9949373Abstract: An array of chip sockets defined by an organic matrix framework surrounding sockets through the organic matrix framework and further comprising a grid of metal vias through the organic matrix framework. In an embodiment, a panel includes an array of chip sockets, each surrounded and defined by an organic matrix framework including a grid of copper vias through the organic matrix framework. The panel includes at least a first region with sockets having a set of dimensions for receiving one type of chip and a second region with sockets and another set of dimensions for receiving a second type of chip.Type: GrantFiled: January 18, 2017Date of Patent: April 17, 2018Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.Inventors: Dror Hurwitz, Alex Huang
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Patent number: 9911700Abstract: A structure consisting of at least one die embedded in a polymer matrix and surrounded by the matrix, and further consisting of at least one through via through the polymer matrix around perimeter of the die, wherein typically the at least one via has both ends exposed and where the die is surrounded by a frame of a first polymer matrix and the at least one through via passes through the frame; the die is positioned with terminals on a lower surface such that the lower surface of the chip is coplanar with a lower surface of the frame, the frame is thicker than the chip, and metal is directly attached to and covers at least part of the upper surface of the chip.Type: GrantFiled: January 26, 2016Date of Patent: March 6, 2018Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.Inventors: Dror Hurwitz, Alex Huang
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Publication number: 20170374747Abstract: A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.Type: ApplicationFiled: June 14, 2017Publication date: December 28, 2017Inventors: Dror Hurwitz, Alex Huang
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Patent number: 9779940Abstract: An embedded die package comprising a die having die contract pads in a passivation layer, the die contact pads being coupled to a first side of a feature layer by an adhesive layer, a layer of pillars extending from a second side of the feature layer, the die, feature layer and the layer of pillars being encapsulated by a dielectric material.Type: GrantFiled: July 1, 2015Date of Patent: October 3, 2017Assignee: Zhuahai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.Inventors: Dror Hurwitz, Alex Huang