Patents by Inventor Durai Vishak Nirmal Ramaswamy

Durai Vishak Nirmal Ramaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240373619
    Abstract: Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.
    Type: Application
    Filed: May 13, 2024
    Publication date: November 7, 2024
    Inventors: Kamal M. Karda, Srinivas Pulugurtha, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20240363763
    Abstract: A device comprises a vertical transistor and a shielding material comprising a conductive material having a P+ type conductivity. The vertical transistor includes an electrode, a dielectric material adjacent to the electrode, and a channel region adjacent to the dielectric material. The channel region comprises a composite structure including at least two semiconductor materials. Also disclosed is a device comprising a first electrically conductive line, vertical transistors overlying the first conductive line, a second electrically conductive line overlying the vertical transistors, and a shielding material positioned between the two adjacent vertical transistors. Each of the vertical transistors comprises a gate electrode, a gate dielectric material on opposite sides of the gate electrode, and a channel region comprising a composite structure including at least two oxide semiconductor materials. The gate dielectric material positions between the gate electrode and the channel region.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Kamal M. Karda, Durai Vishak Nirmal Ramaswamy, Haitao Liu
  • Patent number: 12101946
    Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: November 8, 2023
    Date of Patent: September 24, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Yi Fang Lee, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Ramanathan Gandhi, Karthik Sarpatwari, Scott E. Sills, Sameer Chhajed
  • Publication number: 20240298451
    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells.
    Type: Application
    Filed: April 26, 2024
    Publication date: September 5, 2024
    Applicant: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 12080331
    Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage stru
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: September 3, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni, Richard E Fackenthal, Duane R. Mills
  • Patent number: 12069853
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: August 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy, Haitao Liu
  • Publication number: 20240265960
    Abstract: Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.
    Type: Application
    Filed: March 15, 2024
    Publication date: August 8, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Wayne Kinney
  • Publication number: 20240251543
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a conductive region, a first data line, a second data line, a first memory cell coupled to the first data line and the conductive region, a second memory cell coupled to the second data line and the conductive region, a conductive structure, and a conductive line. The first memory cell includes a first transistor coupled to a second transistor, the first transistor including a first charge storage structure. The second memory cell includes a third transistor coupled to a fourth transistor, the third transistor including a second charge storage structure. The conductive structure is located between and electrically separated from the first and second charge storage structures. The conductive line forms a gate of each of the first, second, third, and fourth transistors.
    Type: Application
    Filed: April 1, 2024
    Publication date: July 25, 2024
    Inventors: Kamal M. Karda, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20240251563
    Abstract: Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.
    Type: Application
    Filed: April 1, 2024
    Publication date: July 25, 2024
    Inventors: Kamal M. Karda, Eric S. Carman, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy, Richard E. Fackenthal, Haitao Liu
  • Patent number: 12040411
    Abstract: A device comprises a first conductive line and a vertical transistor over the first conductive line. The vertical transistor comprises a gate electrode, a gate dielectric material overlying sides of the gate electrode, and a channel region on sides of the gate dielectric material, the gate dielectric material located between the channel region and the gate electrode. The device further comprises a second conductive line overlying a conductive contact of the at least one vertical transistor. Related devices and methods of forming the devices are also disclosed.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: July 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Durai Vishak Nirmal Ramaswamy, Haitao Liu
  • Publication number: 20240233797
    Abstract: Some embodiments include apparatuses and methods operating the apparatuses. One of the apparatuses includes a first data line located over a substrate, a second data line located over the first data line, a third data line located over the second data line and electrically separated from the first and second data lines, and a memory cell coupled to the first, second, and third data lines. The memory cell includes a first material between the first and second data lines and electrically coupled to the first and second data lines; a second material located over the first data line and the first material, the second material electrically separated from the first material and electrically coupled to the third data line; and a memory element electrically coupled to the second material and electrically separated from the first material and first and second data lines.
    Type: Application
    Filed: March 25, 2024
    Publication date: July 11, 2024
    Inventors: Karthik Sarpatwari, Kamal M. Karda, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20240215258
    Abstract: Some embodiments include an integrated assembly having a first bottom electrode adjacent to a second bottom electrode. An intervening region is directly between the first and second bottom electrodes. Capacitor-insulative-material is adjacent to the first and second bottom electrodes. The capacitor-insulative-material is substantially not within the intervening region. Top-electrode-material is adjacent to the capacitor-insulative-material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: February 1, 2024
    Publication date: June 27, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Marcello Mariani, Giorgio Servalli
  • Publication number: 20240196604
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. Each of the first, second, and third data lines includes a length extending in a first direction. Each of the first and second access lines includes a length extending in a second direction. The memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. The first data line is electrically coupled to the first channel region. The second data line is electrically coupled to the first channel region. The third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line.
    Type: Application
    Filed: November 10, 2023
    Publication date: June 13, 2024
    Inventors: Srinivas Pulugurtha, Durai Vishak Nirmal Ramaswamy
  • Publication number: 20240188273
    Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes first, second, and third conductive structures, each having a length in a first direction, first and second memory cells spaced apart from each other in a second direction perpendicular to the first direction, first conductive regions, and second conductive regions. Each of the first and second memory cells includes a first semiconductor portion located on a first level of the apparatus and coupled to the third conductive structure and one of the first and second conductive structures, a second semiconductor portion located on a second level of the apparatus and coupled to one of the first and second conductive structures. The first conductive regions are opposite the first and second semiconductor portions, respectively, of the first memory cell. Second conductive regions are opposite the first and second semiconductor portions, respectively, of the second memory cell.
    Type: Application
    Filed: November 28, 2023
    Publication date: June 6, 2024
    Inventors: Kamal M. Karda, Durai Vishak Nirmal Ramaswamy, Haitao Liu, Karthik Sarpatwari
  • Publication number: 20240188274
    Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a first conductive structure, a second conductive structure, a conductive portion coupled to one of the conductive structures, and a memory cell. The memory cell includes different semiconductor portions located on different levels of the apparatus and separated from each other by a dielectric portion. The first semiconductor portion is coupled to the first and second conductive structures. The second semiconductor portion is coupled to the first conductive structure. The memory cell includes a charge storage structure coupled to the second semiconductor portion. The charge storage structure includes multiple portions. Part of the conductive portion is located between portions of the charge storage structure and separated from the charge storage structure by a dielectric material.
    Type: Application
    Filed: November 29, 2023
    Publication date: June 6, 2024
    Inventors: Kamal M. Karda, Durai Vishak Nirmal Ramaswamy, Karthik Sarpatwari, Haitao Liu
  • Publication number: 20240188302
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a conductive structure; a ferroelectric portion encircling the conductive structure; a charge storage structure encircling the ferroelectric portion; a dielectric portion encircling the charge storage structure; a semiconductor portion encircling the dielectric portion; a first additional conductive structure adjacent a first side of the semiconductor portion; and a second additional conductive structure adjacent a second side of the semiconductor portion, wherein a direction from the first additional conductive structure to the second additional conductive structure is perpendicular to a direction of a length of the conductive structure.
    Type: Application
    Filed: November 27, 2023
    Publication date: June 6, 2024
    Inventors: Kamal M. Karda, Durai Vishak Nirmal Ramaswamy
  • Patent number: 12004354
    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: June 4, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Publication number: 20240172432
    Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: January 31, 2024
    Publication date: May 23, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Yunfei Gao, Sanh D. Tang, Deepak Chandra Pandey
  • Publication number: 20240164113
    Abstract: Methods, systems, and devices for memory structures with voids are described. A memory architecture may include voids between adjacent columns of memory cells. For example, a memory array may be manufactured by forming one or more sacrificial structures, as well as a liner material on sidewalls of the sacrificial structures, extending in the column direction. Memory cells may be formed on the sacrificial structures by patterning a conductive material to form bottom electrodes, forming a ferroelectric material adjacent to the bottom electrodes, and forming a set of plate lines over the ferroelectric material. The sacrificial structures may then be removed to form voids between at least some adjacent columns of memory cells.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 16, 2024
    Inventors: Alessandro Calderoni, Kamal Karda, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11985806
    Abstract: Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 14, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Srinivas Pulugurtha, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy