Patents by Inventor Duy-Phach Vu

Duy-Phach Vu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6143582
    Abstract: The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of higher density and complexity than can be obtained by using conventional multi-chip modules. Processes include the formation of complex multi-function circuitry on common module substrates using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. Circuit modules using integrated transfer/interconnect processes compatible with extremely high density and complexity provide large-area active-matrix displays with on-board drivers and logic in a complete glass-based modules. Other applications are contemplated, such as, displays, microprocessor and memory devices, and communication circuits with optical input and output.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: November 7, 2000
    Assignee: Kopin Corporation
    Inventors: Duy-Phach Vu, Brenda Dingle, Ngwe Cheong
  • Patent number: 6027958
    Abstract: Integrated circuits for use in electronic devices requiring high density packaging are fabricated to provide highly flexible and ultra-thin devices having a variety of applications. The flexible circuits have dimensions up to several centimeters in surface area and thicknesses of a few microns. These circuits are fabricated using transfer techniques which include the removal of VLSI circuits from silicon wafers and mounting of the circuits on application specific substrates.
    Type: Grant
    Filed: July 11, 1996
    Date of Patent: February 22, 2000
    Assignee: Kopin Corporation
    Inventors: Duy-Phach Vu, Brenda Dingle, Ngwe K. Cheong
  • Patent number: 5976953
    Abstract: A multi-layered structure is fabricated in which a microprocessor is configured in different layers and interconnected vertically through insulating layers which separate each circuit layer of the structure. Each circuit layer can be fabricated in a separate wafer or thin film material and then transferred onto the layered structure and interconnected.
    Type: Grant
    Filed: December 8, 1997
    Date of Patent: November 2, 1999
    Assignee: Kopin Corporation
    Inventors: Paul M. Zavracky, Matthew Zavracky, Duy-Phach Vu, Brenda Dingle
  • Patent number: 5793115
    Abstract: A multi-layered structure is fabricated in which a microprocessor is configured in different layers and interconnected vertically through insulating layers which separate each circuit layer of the structure. Each circuit layer can be fabricated in a separate wafer or thin film material and then transferred onto the layered structure and interconnected.
    Type: Grant
    Filed: September 29, 1994
    Date of Patent: August 11, 1998
    Assignee: Kopin Corporation
    Inventors: Paul M. Zavracky, Matthew Zavracky, Duy-Phach Vu, Brenda Dingle
  • Patent number: 5757445
    Abstract: The invention relates to the formation of arrays of thin film transistors (TFT's) on silicon substrates and the dicing and tiling of such substrates for transfer to a common module body. TFT's activate display electrodes formed adjacent the transistors after the tiles have been transferred.
    Type: Grant
    Filed: December 27, 1995
    Date of Patent: May 26, 1998
    Assignee: Kopin Corporation
    Inventors: Duy-Phach Vu, Brenda D. Dingle, Jason E. Dingle, Ngwe Cheong
  • Patent number: 5705424
    Abstract: The present invention relates to methods of fabricating pixel electrodes for active matrix displays including the formation of arrays of transistor circuits in thin film silicon on an insulating substrate and transfer of this active matrix circuit onto an optically transmissive substrate. An array of color filter elements can be formed prior to transfer of the active matrix circuit that are aligned between a light source for the display and the array of pixel electrodes to provide a color display.
    Type: Grant
    Filed: March 21, 1994
    Date of Patent: January 6, 1998
    Assignee: Kopin Corporation
    Inventors: Paul M. Zavracky, Duy-Phach Vu, Brenda Dingle, Matthew Zavracky, Mark B. Spitzer
  • Patent number: 5656548
    Abstract: A multi-layered structure is fabricated in which a microprocessor is configured in different layers and interconnected vertically through insulating layers which separate each circuit layer of the structure. Each circuit layer can be fabricated in a separate wafer or thin film material and then transferred onto the layered structure and interconnected.
    Type: Grant
    Filed: September 19, 1995
    Date of Patent: August 12, 1997
    Assignee: Kopin Corporation
    Inventors: Paul M. Zavracky, Matthew Zavracky, Duy-Phach Vu, Brenda Dingle
  • Patent number: 5578865
    Abstract: A semiconductor fabrication method improves the voltage characteristic of floating-body MOSFETs by creating recombination centers near the source-body junction of the device. A MOSFET is fabricated through the passivation oxidation stage, and a photolithography step is used to expose the source region. Implantation is then performed using one of two types of material. A first type creates electron traps of predetermined energy in the vicinity of the source-body junction. A second type creates defects in the crystalline structure of the semiconductor material. Both implantation types create recombination centers in the material. This allows the discharge through the source-body junction of charges built up in the body region.
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: November 26, 1996
    Assignee: Kopin Corporation
    Inventors: Duy-Phach Vu, Ngwe K. Cheong
  • Patent number: 5539550
    Abstract: Circuit modules including complex multi-function circuitry on common module substrates using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. The modules include integrated transfer/interconnects with extremely high density and complexity with large-area active-matrix liquid crystal displays and on-board drivers and logic in glass-based modules.
    Type: Grant
    Filed: September 9, 1993
    Date of Patent: July 23, 1996
    Assignee: Kopin Corporation
    Inventors: Mark B. Spitzer, Jack P. Salerno, Jeffrey Jacobsen, Brenda Dingle, Duy-Phach Vu, Paul M. Zavracky
  • Patent number: 5499124
    Abstract: The invention relates to the formation of arrays of thin film transistors (TFT's) on silicon substrates and the dicing and tiling of such substrates for transfer to a common module body. TFT's activate display electrodes formed adjacent the transistors after the tiles have been transferred.
    Type: Grant
    Filed: May 8, 1995
    Date of Patent: March 12, 1996
    Inventors: Duy-Phach Vu, Brenda D. Dingle, Jason E. Dingle, Ngwe Cheong
  • Patent number: 5453153
    Abstract: An improved method of zone-melting recrystallizing of a silicon film on an insulator in which the film is implanted and annealed to achieve a reduction of the density of defects within the film.
    Type: Grant
    Filed: March 5, 1992
    Date of Patent: September 26, 1995
    Assignee: Kopin Corporation
    Inventors: John C. C. Fan, Paul M. Zavracky, Jagdish Narayan, Lisa P. Allen, Duy-Phach Vu, Ngwe K. Cheong
  • Patent number: 5420055
    Abstract: A semiconductor fabrication method improves the voltage characteristic of floating-body MOSFETs by creating recombination centers near the source-body junction of the device. A MOSFET is fabricated through the passivation oxidation stage, and a photolithography step is used to expose the source region. Implantation is then performed using one of two types of material. A first type creates electron traps of predetermined energy in the vicinity of the source-body junction. A second type creates defects in the crystalline structure of the semiconductor material. Both implantation types create recombination centers in the material. This allows the discharge through the source-body junction of charges built up in the body region.
    Type: Grant
    Filed: November 16, 1993
    Date of Patent: May 30, 1995
    Assignee: Kopin Corporation
    Inventors: Duy-Phach Vu, Ngwe K. Cheong
  • Patent number: 5377031
    Abstract: The invention relates to the formation of arrays of thin film transistors (TFT's) on silicon substrates and the dicing and tiling of such substrates for transfer to a common module body. TFT's activate display electrodes formed adjacent the transistors after the tiles have been transferred. The invention can be used in a liquid crystal display and may include one or more light shielding layers.
    Type: Grant
    Filed: August 18, 1993
    Date of Patent: December 27, 1994
    Assignee: Kopin Corporation
    Inventors: Duy-Phach Vu, Brenda D. Dingle, Jason E. Dingle, Ngwe Cheong
  • Patent number: 5258325
    Abstract: The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of high density and complexity. Processes include the formation of complex multi-function circuitry on common module substrates using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. Circuit modules using integrated transfer/interconnect processes compatible with extremely high density and complexity provide large-area active-matrix displays with on-board drivers and logic in modules.
    Type: Grant
    Filed: February 13, 1992
    Date of Patent: November 2, 1993
    Assignee: Kopin Corporation
    Inventors: Mark B. Spitzer, Jack P. Salerno, Jeffrey Jacobsen, Brenda Dingle, Duy-Phach Vu, Paul M. Zavracky
  • Patent number: 5256562
    Abstract: The invention relates to the formation of arrays of thin film transistors (TFT's) on silicon substrates and the dicing and tiling of such substrates for transfer to a common module body.
    Type: Grant
    Filed: November 4, 1992
    Date of Patent: October 26, 1993
    Assignee: Kopin Corporation
    Inventors: Duy-Phach Vu, Brenda D. Dingle, Jason E. Dingle, Ngwe Cheong
  • Patent number: 5021119
    Abstract: A method for reducing defects after zone melting and recrystallization of semiconductor films formed on an insulator over a semiconductor substrate by selectively removing portion of a first layer over the semiconductor film, amorphizing the exposed film portion and laterally regrowing the amorphized region.
    Type: Grant
    Filed: October 18, 1990
    Date of Patent: June 4, 1991
    Assignee: Kopin Corporation
    Inventors: John C.C. Fan, Paul M. Zavracky, Jagdish Narayan, Lisa P. Allen, Duy-Phach Vu
  • Patent number: 4944835
    Abstract: An improved method of forming seed openings for zone-melting and recrystallization of polysilicon film on an insulator over silicon (SOI) is described. This method comprises forming a narrow discontinuous pattern of seed openings formed by an overlapping sub-pattern of discontinuous shaped openings. Alternatively, in an edge bead seed embodiment, a resist is removed from an SOI precursor structure, comprising an insulator on an Si wafer, thus exposing the peripheral edge of the insulator. The exposed insulator is then also removed to provide a peripheral edge seed opening to the underlying Si wafer.
    Type: Grant
    Filed: March 30, 1989
    Date of Patent: July 31, 1990
    Assignee: Kopin Corporation
    Inventors: Lisa P. Allen, Duy-Phach Vu, Michael W. Batty, Richard H. Morrision, Jr., Paul M. Zavracky
  • Patent number: 4922315
    Abstract: The present invention relates to silicon-on-insulator (SOI) gated lateral bipolar transistors that are CMOS compatible. A method is described wherein a heavily doped region is implanted into the base after gate formation to provide a low resistance path to the base contact. A lightly doped region is also provided underneath the gate to minimize base-collector capacitance.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: May 1, 1990
    Assignee: Kopin Corporation
    Inventor: Duy-Phach Vu
  • Patent number: 4914491
    Abstract: A junction field effect transistor formed on insulator substrates particularly oxide substrates and having a polysilicon vertical control gate region formed of a cross member and two end members orthogonal thereto. The vertical control gate is formed over an n-channel in a Si island, the n-channel is located beneath the cross member, with p.sup.+ junction gate regions laterally disposed on either side of the n-channel and n.sup.+ drain and gate regions laterally orthogonal thereto in Si island.
    Type: Grant
    Filed: June 29, 1989
    Date of Patent: April 3, 1990
    Assignee: Kopin Corporation
    Inventor: Duy-Phach Vu
  • Patent number: 4885052
    Abstract: An improved method of zone-melting and recrystallizing of polysilicon film on an insulator over silicon is described.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: December 5, 1989
    Assignee: Kopin Corporation
    Inventors: John C. C. Fan, Paul M. Zavracky, Jagdish Narayan, Lisa P. Allen, Duy-Phach Vu