Patents by Inventor E. Yu

E. Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10163500
    Abstract: Error correction systems and methods for improving sense matching conditions between hard-bit read (HBR) information and soft-bit read (SBR) information. For HBRs, a given set of sense conditions can include a discharged bit line of one or more cells that discharged during a previous HBR. For SBRs, a given set of sense conditions can include loading latches of the sense amplifiers for corresponding cells are with sense results of the previous SBR strobe when the corresponding cells discharged during a previous SBR strobe or loading the latches of the sense amplifiers with sense results of a previous HBR when the corresponding cells discharged during the previous HBR.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Erwin E. Yu, William C. Filipiak, Dheeraj Srinivasan
  • Publication number: 20180366203
    Abstract: Apparatus and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.
    Type: Application
    Filed: August 24, 2018
    Publication date: December 20, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Luyen Vu, Kalyan C. Kavalipurau, Jae-Kwan Park, Erwin E. Yu
  • Publication number: 20180336155
    Abstract: The invention provides a circuit structure sharing the same memory, where the circuit structure includes a first volatile memory, a system chip and a signal processing chip. The system chip is connected to the first volatile memory via a first connection interface. The signal processing chip is connected to the system chip via a second connection interface. A memory controller is disposed in the system chip and connected to the first connection interface and the second connection interface. The signal processing chip transmits a first access command to the memory controller via the second connection interface, and the memory controller accesses the first volatile memory via the first connection interface according to the first access command and transmits the access result of the first access command to the signal processing chip via the second connection interface.
    Type: Application
    Filed: May 22, 2018
    Publication date: November 22, 2018
    Applicant: ALi Corporation
    Inventors: Jian-Xin Li, Dong e Yu, Han-jun Li
  • Patent number: 10127988
    Abstract: Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 13, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Luyen Vu, Kalyan C. Kavalipurau, Jae-Kwan Park, Erwin E. Yu
  • Publication number: 20180061497
    Abstract: Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.
    Type: Application
    Filed: August 26, 2016
    Publication date: March 1, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Luyen Vu, Kalyan C. Kavalipurau, Jae-Kwan Park, Erwin E. Yu
  • Patent number: 9633744
    Abstract: Systems, apparatuses and methods may provide for determining a magnitude of a bounce voltage on a source line associated with one or more memory cells and conducting, if the magnitude of the bounce voltage exceeds a threshold, a coarse-level program verification and a fine-level program verification of the one or more memory cells. Additionally, if the magnitude of the bounce voltage does not exceed the threshold, only the fine-level program verification of the one or more memory cells may be conducted. In one example, the coarse-level program verification is bypassed if the magnitude of the bounce voltage does not exceed the threshold.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Kalyan C. Kavalipurapu, Jae-Kwan Park, Erwin E. Yu, Michele Piccardi
  • Publication number: 20170084347
    Abstract: Systems, apparatuses and methods may provide for determining a magnitude of a bounce voltage on a source line associated with one or more memory cells and conducting, if the magnitude of the bounce voltage exceeds a threshold, a coarse-level program verification and a fine-level program verification of the one or more memory cells. Additionally, if the magnitude of the bounce voltage does not exceed the threshold, only the fine-level program verification of the one or more memory cells may be conducted. In one example, the coarse-level program verification is bypassed if the magnitude of the bounce voltage does not exceed the threshold.
    Type: Application
    Filed: September 18, 2015
    Publication date: March 23, 2017
    Applicant: INTEL CORPORATION
    Inventors: Kalyan C. Kavalipurapu, Jae-Kwan Park, Erwin E. Yu, Michele Piccardi
  • Patent number: 8179726
    Abstract: A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array using a minimum number of programming pulses.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: May 15, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Erwin E. Yu, Ebrahim Abedifard, Frederick T. Jaffin, Uday Chandrasekhar
  • Publication number: 20110247463
    Abstract: A socket wrench assembly includes three drive shanks each having a bore and each having a socket member attached to the outer end, and each having a smaller compartment and a greater non-circular chamber formed in the socket member, and the inner end portions of the drive shanks are secured together to form a Y-shaped or T-shaped structure for allowing either of the drive shanks to be driven or rotated by the other drive shanks with a greater driving torque, and the chambers of the socket members include inner diameters different from each other for receiving or engaging with or for driving tool members of different dimensions or sizes.
    Type: Application
    Filed: April 13, 2010
    Publication date: October 13, 2011
    Inventor: Hsiu E. Yu
  • Publication number: 20110235429
    Abstract: A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array using a minimum number of programming pulses.
    Type: Application
    Filed: June 7, 2011
    Publication date: September 29, 2011
    Inventors: Erwin E. Yu, Ebrahim Abedifard, Frederick T. Jaffin, Uday Chandrasekhar
  • Patent number: 7974129
    Abstract: A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array using a minimum number of programming pulses.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: July 5, 2011
    Assignee: Micron Technologies, Inc.
    Inventors: Erwin E. Yu, Ebrahim Abedifard, Frederick T. Jaffin, Uday Chandrasekhar
  • Patent number: 7951374
    Abstract: Methods of enhancing antitumor activity of an immune cell comprising contacting the immune cell with a Stat3 inhibitor are described. Also described are methods of killing a tumor cell or inhibiting tumor growth in a subject comprising contacting an immune cell of the subject with a Stat3 inhibitor.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: May 31, 2011
    Assignees: University of South Florida, The Johns Hopkins University
    Inventors: Hua E. Yu, Richard Jove, Marcin Kortylewski, Drew M. Pardoll
  • Publication number: 20100247427
    Abstract: Provided herein are methods of enhancing the radiation response of a cell expressing activated Stat1, Stat3, or Stat5. Methods for synergistically affecting a cell expressing activated Stat1, Stat3, or Stat5 are also described. The described methods may also be used to synergistically affect or enhance the radiation response of a cell in a subject.
    Type: Application
    Filed: October 16, 2006
    Publication date: September 30, 2010
    Applicant: University of South Florida
    Inventors: Javier F. Torres-Roca, Douglas P. Calvin, Madhavi Sekharam, Hua E. Yu, Richard Jove
  • Publication number: 20100110797
    Abstract: A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array using a minimum number of programming pulses.
    Type: Application
    Filed: January 12, 2010
    Publication date: May 6, 2010
    Inventors: Erwin E. Yu, Ebrahim Abedifard, Frederick T. Jaffin, Uday Chandrasekhar
  • Patent number: 7663925
    Abstract: A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array using a minimum number of programming pulses.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: February 16, 2010
    Assignee: Micron Technology Inc.
    Inventors: Erwin E. Yu, Ebrahim Abedifard, Frederick T. Jaffin, Uday Chandrasekhar
  • Publication number: 20060212992
    Abstract: A composition for a damp hand donnable glove using a novel coating. The novel coating results in the formulation of domains of variable size and height. The coating has a polyurethane polymer, and aqueous dispersion and a surfactant.
    Type: Application
    Filed: May 18, 2006
    Publication date: September 28, 2006
    Inventors: Jeffery Nile, Stanley Gromelski, Paul Cacioli, Richard Cox, E. Yu
  • Patent number: 7029361
    Abstract: A finger puppet toy sits comfortably on a finger of a child, and generates a sound when the finger is tapped against a hard object, such as a desk or a table-top. The sound may be a voice, an animal sound, an animal voice sound, a musical note, or any of the above sounds in the key of a musical note. The head of the puppet toy articulates about a shaft when the child articulates the finger, and the head may thus appear to move while the sound is generated. Multiple toys worn on one or more hands and having different musical notes may be tapped in sequence to play a melody.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: April 18, 2006
    Assignee: The Marketing Store Worldwide, L.P.
    Inventors: Amy M. Seibert, Ruth E. Synowic, Michael G. Gierek, Thomas Tretter, Kevin L. Taylor, Julie E. Yu
  • Patent number: D866714
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: November 12, 2019
    Inventor: Li E Yu
  • Patent number: D870854
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: December 24, 2019
    Inventor: Li E Yu
  • Patent number: D871550
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: December 31, 2019
    Inventor: Li E Yu