Abstract: A circuit arrangement and method for a data processing system for executing a plurality of tasks with a central processing unit having a processing capacity allocated to the processing unit; the circuit arrangement being configured to allocate the processing unit to the specific tasks in a time-staggered manner for processing, so that the tasks are processed in an order to be selected and tasks not having a current processing request are skipped over in the order during the processing; the circuit arrangement including a prioritization order control unit to determine the order in which the tasks are executed; and in response to each selection of a task for processing, the order of the tasks being redetermined and the selection being controlled so that for a number N of tasks, a maximum of N time units elapse until an active task is once more allocated processing capacity by the processing unit.

Abstract: A timer module having a status register is connectable to an external arithmetic unit and generates at least one activity signal for an internal signal of the timer module and/or an internal unit of the timer module and/or a process within the internal unit, and enters an activity status into a status register in the event of a determined activity, and allows the activity status to be polled and reset by the external arithmetic unit at times determined by the external arithmetic unit. Furthermore, the activity status entered into the status register remains until it is reset by the external arithmetic unit.

Abstract: A method for assessing an output of a random number generator which is provided by two phase-locked loops of the random number generator includes: receiving, by a checking system, the output of the random number generator for at least two sampling cycle, wherein for each sampling cycle (i) the output of the random generator includes a sequence of sample values between a starting value and an end value, and (ii) all sample values between the starting value and the end value in the respective cycle are entered into a signature; and comparing, by the checking system, the signatures from the at least two sampling cycles to one another.

Abstract: In a method for checking an output of a random number generator which includes at least one random source, the frequency of occurrence of at least one bit assignment is counted and established in a correlation with the total number of values which are taken into account.

Abstract: A method and an assemblage for checking an output of a random generator are presented. In the method, signatures that are respectively created from a sequence of sampled values are compared with one another.

Abstract: A method and as assemblage for post-processing an output of a random source of a random generator are presented. In the method, an output signal of the random source is compressed, thereby yielding a sequence of compressed signal values that are checked in terms of their distribution.

Abstract: A vehicle-supported data processing system includes a plurality of processing units communicating with one another via a bus system, which are each supplied with operating power by at least one of the at least two different vehicle electrical systems. Multiple transmitter units for control information and multiple receiver units for the control information are among the processing units. The bus system is a ring bus, in which each processing unit is connected to at least two adjacent processing units by a bus segment in each case. The ring bus is divided, by potential separating devices, which are incorporated in the bus segments which connect processing units powered by different vehicle electrical systems, into a number of sections, which is smaller than the number of the processing units.

Abstract: A circuit configuration for a data processing system and a corresponding method for executing multiple tasks by way of a central processing unit having a processing capacity assigned to the processing unit, the circuit configuration being configured to distribute the processing capacity of the processing unit uniformly among the respective tasks, and to process the respective tasks in time-offset fashion until they are respectively executed.

Abstract: A nonlinear feedback shift register for creating a signature for cryptographic applications includes a sequence of series-connected flip-flops which are connected to each other for forming at least one polynomial, with the aid of at least one signal feedback having at least one operator. The flip-flops are connected to at least one switching operator for forming at least two different polynomials, the switching operator switching between the polynomials as a function of an input signal. A method for nonlinear signature formation is also provided.

Abstract: A method for generating a one-way function, as well as a circuit arrangement, which implements the one-way function, are set forth.

Abstract: A method and a device for generating a random output bit sequence are put forth. In the case of these, an input is inputted into a set-up of finite state machines. The set-up ascertains an output on the basis of the input; the input being inputted into the set-up, linked to a one-way function.

Abstract: A method is described for detecting a correlation between at least two ring oscillators and to a system for carrying out the method. In the method a memory field is used in which combinations of concatenations are each assigned a bit.

Abstract: A method for detecting a correlation of a first ring oscillator with a second ring oscillator and a system for carrying out the method are provided. In the method, combinations of concatenations are compared to chronologically preceding concatenations.

Abstract: A method and a circuit system for checking an m out of n code are provided. The method uses a code checker, to which at least one code reducer is assigned, a reduction of the code word width to in each case half being carried out using the at least one code reducer until a 1 out of x (x=n/2, n/4, n/8 . . . ) code or another code which is not reducible further in this way is provided, each step of the code reducer additionally being connected to different bits of a counter, the 1 out of x code or the code which is not further reducible being checked and additionally the signal pairs of each step being checked.

Abstract: A method and a random bit generator for generating a random output bit sequence. In this method, a configuration of 2n state machines is used, the state machines each including n state bits, each state machine always assuming a different state than the other state machines of the configuration, an input signal being supplied to the input end of the state machines, and these each generating n signature bits, which together form a signature bit sequence, as a function of their state, the random output bit sequence being generated by selection of individual bits from the signature bit sequences of all state machines of the configuration.

Abstract: A method and a circuit system are provided for securely checking a first code word. The method uses at least one code checker, and provides that the first code word to be checked is transferred into a second code word prior to entry into the code checker.

Abstract: A method and an assemblage for generating random numbers. In the method, at a ring oscillator that comprises an odd number of inverting elements, values are picked off at at least two sampling points, an odd number of inverting elements being present in each case between at least two directly successive sampling points.

Abstract: An assemblage for monitoring an output of a random generator is provided, which assemblage compares chronologically successive sample values at a sampling point with one another in order to detect a relationship of the compared sample values with one another.

Abstract: A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method.

Abstract: A hardware data processing unit has at least one base transmitter module, at least one logic unit, and at least one routing unit. The base transmitter module provides base values of a physical variable. The routing unit arbitrates a group of data nodes associated therewith in a determined sequence. The duration of a cycle is defined by a complete iteration of the determined sequence. The hardware data processing unit has a mechanism that checks the cycle duration. The mechanism carries out a first blocked access to a determined data node of the group to capture and store a first base value from the base transmitter module. The mechanism carries out a second blocked access to the determined data node to capture and store a second base value. The mechanism determines a difference between the first and the second base values.