Abstract: A device and method for switching over in a computer system having at least two execution units are provided, in which switchover units are included which are designed in such a way that they switch between at least two operating modes, a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode. A programmable interrupt controller is assigned to each execution unit, and a storage element is included, in which information is stored that describes at least parts of a configuration of at least one of these interrupt controllers.

Abstract: In a method for error handling in transmission of a datum over a communications system, at least two data words consisting of bits are generated for the datum in accordance with a predefined coding rule, and one of the generated data words is selected taking into consideration a running digital sum formed over the corresponding data word, and the running digital sum of the selected data word is used for the formation of a first running digital sum. The selected data word is converted into a code data word, and a bit of the data word is in each case assigned a two-bit string with two different single-bit values. The code data word and the first running digital sum are transmitted. The received code data word is examined to ascertain whether an erroneous two-bit string exists, in which case the error is corrected using the first running digital sum.

Abstract: A method for establishing an initial state in a computer system having at least two execution units, a switchover between a performance mode and a compare mode being performed, and during the switchover from the performance mode to the compare mode, an initial state for the compare mode being generated, wherein memories or memory areas that are potentially to be adapted for the initial state are provided with an identifier that indicates whether or not the data and/or instructions in these memories or memory areas must be modified for the initial state.

Abstract: A device and method for storing data and/or instructions in a computer system having at least two processing units and at least one first memory or memory area for data and/or instructions, wherein a second memory or memory area is included in the device, the device being designed as a cache memory system and equipped with at least two separate ports, and the at least two processing units accessing via these ports the same or different memory cells of the second memory or memory area, the data and/or instructions from the first memory system being stored temporarily in blocks.

Abstract: A method and device for data processing having at least three identical or similar execution units, wherein at least one comparator exists and at least two execution units are grouped such that the output signals of the at least two execution units are connected with the at least one comparator and compared.

Abstract: A method and device for controlling a computer system having at least two execution units, a switchover taking place between at least two operating modes, and a first operating mode corresponds to a compare mode, and a second operating mode corresponds to a performance mode, wherein at least one set of run-time objects is defined, and a control program is provided, in particular a scheduler, which assigns resources of the computer system to the run-time objects as a function of an item of information regarding the operating mode.

Abstract: A method for comparing data in a computer system having at least two execution units, the comparison of the data taking place in a comparison unit and each execution unit processing input data and generating output data, wherein one execution unit specifies to the comparison unit that the next piece of output data is to be compared to a piece of output data of the at least second execution unit, and thereupon a comparison of the at least two output data takes place.

Abstract: A data processing device is described having a first receive data input unit for inputting a first receive data stream into the data processing device, at least one second receive data input unit for inputting at least one second receive data stream and a clock recovery unit for recovering a clock signal from the first receive data stream and/or the at least one second receive data stream. A control device controls the clock recovery unit as a function of either the first receive data stream or of one of the at least second receive data streams and a delay unit delays the at least one second receive data stream with respect to the first receive data stream in such a way that the first receive data stream is synchronized with the at least one second receive data stream.

Abstract: A device and a method are for forming a signature for use in a transmitter unit or a receiver unit of a communication system. To speed up the formation of a signature and thus the data transfer between a computer unit (e.g., a microcontroller) and a communication controller of the transmitter unit or the receiver unit, the device is arranged as hardware and the device forms the signature for data which are to be transferred from a computer unit of the transmitter unit to a communication controller of the transmitter unit for the purpose of data transmission via a communication medium of the communication system or which are to be transferred from a communication controller of the receiver unit to a computer unit of the receiver unit for further processing.

Abstract: A device and method for performing switchover operations in a computer system having at least two execution units, a changeover switch being provided which switches between at least two operating modes, a first operating mode corresponding to a comparison mode, and a second operating mode corresponding to a performance mode, in addition, a comparator being provided which is activated in the comparison mode, in which an arrangement provides desired switchover detection, the arrangement for desired switchover detection controlling the changeover switch in order to switch from one operating mode to another.

Abstract: A method and a device are provided for performing switching and data comparison in a computer system having at least two processing units which each process data at a specified clock pulse, in which a switchover arrangement is provided and switching takes place between at least two operating modes, and a comparison unit is provided. A first operating mode corresponding to a compare mode is provided, and a second operating mode corresponding to a performance mode is provided. A synchronization arrangement is provided which assigns to the specifiable data a clock pulse information as a function of a processing unit, and at least the comparison unit takes into consideration this clock pulse information in the corresponding data.

Abstract: A method and device for generating a signal in a computer system having a plurality of components, at least two execution units being provided as two components, and a switchover means being provided as an additional component, in the computer system, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode, wherein, in one component of the computer system, a mode signal, indicative of the current operating mode, and/or changes in a mode signal are generated, and at least the changes in the mode signal and/or the mode signal itself are made available outside of the component.

Abstract: A device for correcting errors in a system having at least two execution units having registers is presented, the registers being designed for recording data. The device has comparison device(s) that are set up such that through a comparison of data that are provided for storage in the registers, a deviation and thus an error may be ascertained. Furthermore, at least one shadow register that is set up such that data concerning the data of the registers may be stored therein, and device(s) are provided for restoring error-free data in at least one register on the basis of the data in the at least one shadow register when an error is detected. This device may be used to improve the safety of a multicore processor.

Abstract: A method for processing data words and/or instructions, a distinction being made, in the processing, between at least two operating modes, and a first operating mode corresponding to a compare mode and a second operating mode corresponding to a performance mode, in the compare mode, a comparator unit being activated and this comparator unit being deactivated in the performance mode, wherein the comparator unit is activated for the compare mode as a function of two equal data words and/or instructions getting to be processed and the at least equal data words and/or instructions in each case being distributed by a control unit to the at least two execution units.

Abstract: A method and a device for performing switchover operations and for comparing data in a computer system having at least three processing units are provided, in which switchover unit is provided, a switchover operations being carried out between at least two operating modes, and a comparison unit is provided. A first operating mode corresponding to a comparison mode, and a second operating mode corresponding to a performance mode are provided. Provision is made in the comparison mode for a voting, at least as a two-out-of-three weighting, and a control unit is provided which may be used to set the voting.

Abstract: A method and device for performing switchover operations in a computer system having at least two processing units, a switchover device, and a comparison device, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode, information being compared in the comparison mode. In the case of asynchronous operation of the at least two processing units in the comparison mode, a synchronization signal is applied to one interrupt input of at least one of the processing units.

Abstract: A method and a device are provided for separating the processing of program code in a computer system having at least two execution units, in which method and device switching over takes place between at least two operating modes, and a first operating mode corresponds to a comparison mode and a second operating mode corresponds to a performance mode, and the at least two execution units process the same program code in the comparison mode. When there is a switchover from the comparison mode to the performance mode, a separation in the program code takes place in that each execution unit has an identifier assigned to it, and, as a function of the identifier, different program code is assigned to at least two execution units.

Abstract: A method and a device for generating codes in the transmission of data via a communications system having at least two subscribers, in which a first subscriber receives at least one data word and forwards the data word or an at least partially changed data word to at least one second subscriber, the data being represented as bits which are able to assume two different values, and at least two bits of a data word are coded in at least three bits in such a way that in the three coded bits always at least two bits of the same value follow each other and that, after the reception of one or two of the three coded bits, one may already be able to decide which first code bit is to be emitted.

Abstract: A device and a method for forming a signature, a predefined number of shift registers being provided, to which input data to be tested is applied bit-by-bit and in parallel as successive data words and which serially shift the input data forward in a predefinable cycle, a signature being formed in the shift registers after a certain number of data words and cycles, a code generator which generates at least one additional bit position in at least one additional shift register from each data word in the signature also being provided.

Abstract: A method and device for switching over in a computer system having at least two execution units, switching being carried out between at least two operating modes, and the operating modes corresponding to states of the computer system, a first state corresponding to a comparison mode and a second state corresponding to a performance mode, so that events may occur by which the computer system can attain an otherwise undefined state, in which, in response to the occurrence of any such event, the second state is assumed, which corresponds to a performance mode.